167 lines
7.7 KiB
Tcl
167 lines
7.7 KiB
Tcl
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# ad9250-xcvr
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add_instance avl_ad9250_xcvr avl_adxcvr
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set_instance_parameter_value avl_ad9250_xcvr {ID} {0}
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set_instance_parameter_value avl_ad9250_xcvr {TX_OR_RX_N} {0}
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set_instance_parameter_value avl_ad9250_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
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set_instance_parameter_value avl_ad9250_xcvr {LANE_RATE} {5000.0}
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set_instance_parameter_value avl_ad9250_xcvr {PLLCLK_FREQUENCY} {2500.0}
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set_instance_parameter_value avl_ad9250_xcvr {REFCLK_FREQUENCY} {250.0}
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set_instance_parameter_value avl_ad9250_xcvr {CORECLK_FREQUENCY} {125.0}
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set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_LANES} {4}
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set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_CONVS} {4}
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set_instance_parameter_value avl_ad9250_xcvr {FRM_BCNT} {4}
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set_instance_parameter_value avl_ad9250_xcvr {FRM_SCNT} {1}
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set_instance_parameter_value avl_ad9250_xcvr {MF_FCNT} {32}
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set_instance_parameter_value avl_ad9250_xcvr {HD} {0}
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add_connection sys_clk.clk avl_ad9250_xcvr.sys_clk
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add_connection sys_clk.clk_reset avl_ad9250_xcvr.sys_resetn
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add_interface rx_ref_clk clock sink
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set_interface_property rx_ref_clk EXPORT_OF avl_ad9250_xcvr.ref_clk
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add_interface rx_data_0 conduit end
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set_interface_property rx_data_0 EXPORT_OF avl_ad9250_xcvr.rx_data_0
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add_interface rx_data_1 conduit end
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set_interface_property rx_data_1 EXPORT_OF avl_ad9250_xcvr.rx_data_1
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add_interface rx_data_2 conduit end
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set_interface_property rx_data_2 EXPORT_OF avl_ad9250_xcvr.rx_data_2
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add_interface rx_data_3 conduit end
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set_interface_property rx_data_3 EXPORT_OF avl_ad9250_xcvr.rx_data_3
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add_interface rx_sysref conduit end
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set_interface_property rx_sysref EXPORT_OF avl_ad9250_xcvr.sysref
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add_interface rx_sync conduit end
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set_interface_property rx_sync EXPORT_OF avl_ad9250_xcvr.sync
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add_interface rx_ip_sof conduit end
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set_interface_property rx_ip_sof EXPORT_OF avl_ad9250_xcvr.ip_sof
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add_interface rx_ip_data avalon_streaming source
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set_interface_property rx_ip_data EXPORT_OF avl_ad9250_xcvr.ip_data
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# ad9250-xcvr
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add_instance axi_ad9250_xcvr axi_adxcvr
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set_instance_parameter_value axi_ad9250_xcvr {ID} {0}
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set_instance_parameter_value axi_ad9250_xcvr {TX_OR_RX_N} {0}
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set_instance_parameter_value axi_ad9250_xcvr {NUM_OF_LANES} {4}
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add_connection sys_clk.clk axi_ad9250_xcvr.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9250_xcvr.s_axi_reset
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add_connection axi_ad9250_xcvr.if_up_rst avl_ad9250_xcvr.rst
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add_connection avl_ad9250_xcvr.ready axi_ad9250_xcvr.ready
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add_connection axi_ad9250_xcvr.core_pll_locked avl_ad9250_xcvr.core_pll_locked
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# ad9250
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add_instance axi_ad9250_core_0 axi_ad9250
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set_instance_parameter_value axi_ad9250_core_0 {ID} {0}
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add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_0.if_rx_clk
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add_interface rx_ip_sof_0 conduit end
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set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9250_core_0.if_rx_sof
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add_interface rx_ip_data_0 avalon_streaming sink
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set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9250_core_0.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9250_core_0.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_core_0.s_axi_clock
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add_instance axi_ad9250_core_1 axi_ad9250
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set_instance_parameter_value axi_ad9250_core_1 {ID} {1}
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add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_1.if_rx_clk
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add_interface rx_ip_sof_1 conduit end
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set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9250_core_1.if_rx_sof
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add_interface rx_ip_data_1 avalon_streaming sink
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set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9250_core_1.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9250_core_1.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock
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# ad9250-pack
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add_instance util_ad9250_cpack_0 util_cpack
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set_instance_parameter_value util_ad9250_cpack_0 {CHANNEL_DATA_WIDTH} {32}
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set_instance_parameter_value util_ad9250_cpack_0 {NUM_OF_CHANNELS} {2}
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add_connection sys_clk.clk_reset util_ad9250_cpack_0.if_adc_rst
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add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_0.if_adc_clk
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add_connection axi_ad9250_core_0.adc_ch_0 util_ad9250_cpack_0.adc_ch_0
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add_connection axi_ad9250_core_0.adc_ch_1 util_ad9250_cpack_0.adc_ch_1
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add_instance util_ad9250_cpack_1 util_cpack
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set_instance_parameter_value util_ad9250_cpack_1 {CHANNEL_DATA_WIDTH} {32}
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set_instance_parameter_value util_ad9250_cpack_1 {NUM_OF_CHANNELS} {2}
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add_connection sys_clk.clk_reset util_ad9250_cpack_1.if_adc_rst
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add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_1.if_adc_clk
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add_connection axi_ad9250_core_1.adc_ch_0 util_ad9250_cpack_1.adc_ch_0
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add_connection axi_ad9250_core_1.adc_ch_1 util_ad9250_cpack_1.adc_ch_1
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# ad9250-dma
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add_instance axi_ad9250_dma_0 axi_dmac
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set_instance_parameter_value axi_ad9250_dma_0 {ID} {0}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_SRC} {2}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9250_dma_0 {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_DEST} {64}
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add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_0.if_fifo_wr_clk
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add_connection util_ad9250_cpack_0.if_adc_valid axi_ad9250_dma_0.if_fifo_wr_en
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add_connection util_ad9250_cpack_0.if_adc_sync axi_ad9250_dma_0.if_fifo_wr_sync
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add_connection util_ad9250_cpack_0.if_adc_data axi_ad9250_dma_0.if_fifo_wr_din
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add_connection axi_ad9250_dma_0.if_fifo_wr_overflow axi_ad9250_core_0.if_adc_dovf
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add_connection sys_clk.clk_reset axi_ad9250_dma_0.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_dma_0.s_axi_clock
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add_connection sys_dma_clk.clk_reset axi_ad9250_dma_0.m_dest_axi_reset
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add_connection sys_dma_clk.clk axi_ad9250_dma_0.m_dest_axi_clock
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add_instance axi_ad9250_dma_1 axi_dmac
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set_instance_parameter_value axi_ad9250_dma_1 {ID} {1}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_SRC} {2}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9250_dma_1 {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_DEST} {64}
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add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_1.if_fifo_wr_clk
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add_connection util_ad9250_cpack_1.if_adc_valid axi_ad9250_dma_1.if_fifo_wr_en
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add_connection util_ad9250_cpack_1.if_adc_sync axi_ad9250_dma_1.if_fifo_wr_sync
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add_connection util_ad9250_cpack_1.if_adc_data axi_ad9250_dma_1.if_fifo_wr_din
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add_connection axi_ad9250_dma_1.if_fifo_wr_overflow axi_ad9250_core_1.if_adc_dovf
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add_connection sys_clk.clk_reset axi_ad9250_dma_1.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_dma_1.s_axi_clock
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add_connection sys_dma_clk.clk_reset axi_ad9250_dma_1.m_dest_axi_reset
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add_connection sys_dma_clk.clk axi_ad9250_dma_1.m_dest_axi_clock
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# core-clock
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add_instance rx_core_clk altera_clock_bridge
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add_connection avl_ad9250_xcvr.core_clk rx_core_clk.in_clk
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add_interface rx_core_clk clock source
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set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk
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# addresses
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ad_cpu_interconnect 0x00010000 avl_ad9250_xcvr.phy_reconfig_0
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ad_cpu_interconnect 0x00012000 avl_ad9250_xcvr.phy_reconfig_1
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ad_cpu_interconnect 0x00014000 avl_ad9250_xcvr.phy_reconfig_2
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ad_cpu_interconnect 0x00016000 avl_ad9250_xcvr.phy_reconfig_3
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ad_cpu_interconnect 0x0001b000 avl_ad9250_xcvr.core_pll_reconfig
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ad_cpu_interconnect 0x0001c000 avl_ad9250_xcvr.ip_reconfig
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ad_cpu_interconnect 0x00030000 axi_ad9250_xcvr.s_axi
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ad_cpu_interconnect 0x00040000 axi_ad9250_core_0.s_axi
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ad_cpu_interconnect 0x00050000 axi_ad9250_core_1.s_axi
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ad_cpu_interconnect 0x00060000 axi_ad9250_dma_0.s_axi
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ad_cpu_interconnect 0x00070000 axi_ad9250_dma_1.s_axi
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# dma interconnects
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ad_dma_interconnect axi_ad9250_dma_0.m_dest_axi
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ad_dma_interconnect axi_ad9250_dma_1.m_dest_axi
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# interrupts
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ad_cpu_interrupt 11 axi_ad9250_dma_0.interrupt_sender
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ad_cpu_interrupt 12 axi_ad9250_dma_1.interrupt_sender
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