Laszlo Nagy 20161cf458 xilinx/axi_adxcvr/axi_adxcvr_mdrp: Fix read if all channels are selected ... If all channels are selected for read the values and ready signals from every transceiver are combined. Each element merges his signals with the previous. The first element of the chain must assume the previous channel is always ready.		2021-06-25 14:15:59 +03:00
..
axi_adcfifo	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
axi_adxcvr	xilinx/axi_adxcvr/axi_adxcvr_mdrp: Fix read if all channels are selected	2021-06-25 14:15:59 +03:00
axi_dacfifo	axi_dacfifo: Allow datawidths larger than the AXI datawidth	2020-02-18 11:19:02 +02:00
axi_xcvrlb	axi_xcvrlb: added new parameters to IP	2020-01-07 16:18:33 +02:00
common	library: Move ad_iobuf to the common library, as it's not Xilinx specific	2020-11-02 16:13:35 +02:00
util_adxcvr	util_adxcvr: Hook up RXPROGDIVRESET	2021-06-10 09:53:43 +03:00
util_clkdiv	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00