196 lines
7.0 KiB
Verilog
196 lines
7.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// this is a sine function (approximate), the basic idea is to approximate sine as a
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// polynomial function (there are a lot of stuff about this on the web)
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`timescale 1ns/100ps
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module ad_dds_sine (
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// sine = sin(angle)
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clk,
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angle,
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sine,
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ddata_in,
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ddata_out);
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// parameters
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parameter DELAY_DATA_WIDTH = 16;
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localparam DW = DELAY_DATA_WIDTH - 1;
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// sine = sin(angle)
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input clk;
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input [15:0] angle;
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output [15:0] sine;
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input [DW:0] ddata_in;
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output [DW:0] ddata_out;
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// internal registers
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reg [DW:0] ddata_s2_i = 'd0;
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reg data_msb_s2_i = 'd0;
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reg [15:0] data_delay_s2_i = 'd0;
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reg [15:0] data_sine_s2_i = 'd0;
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reg [DW:0] ddata_s2 = 'd0;
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reg data_msb_s2 = 'd0;
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reg [15:0] data_sine_s2 = 'd0;
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reg [DW:0] ddata_s3_i = 'd0;
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reg data_msb_s3_i = 'd0;
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reg [15:0] data_delay_s3_i = 'd0;
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reg [15:0] data_sine_s3_i = 'd0;
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reg [DW:0] ddata_s4 = 'd0;
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reg data_msb = 'd0;
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reg [14:0] data_sine_p = 'd0;
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reg [14:0] data_sine_n = 'd0;
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reg [DW:0] ddata_out = 'd0;
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reg [15:0] sine = 'd0;
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// internal signals
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wire [DW:0] ddata_s1_s;
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wire data_msb_s1_s;
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wire [31:0] data_sine_s1_s;
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wire [DW:0] ddata_s2_i_s;
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wire data_msb_s2_i_s;
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wire [15:0] data_delay_s2_i_s;
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wire [31:0] data_sine_s2_i_s;
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wire [DW:0] ddata_s2_s;
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wire data_msb_s2_s;
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wire [31:0] data_sine_s2_s;
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wire [DW:0] ddata_s3_i_s;
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wire data_msb_s3_i_s;
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wire [15:0] data_delay_s3_i_s;
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wire [31:0] data_sine_s3_i_s;
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wire [DW:0] ddata_s3_s;
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wire data_msb_s3_s;
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wire [31:0] data_sine_s3_s;
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// level 1 (intermediate) A*x;
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ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s1 (
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.clk (clk),
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.data_a ({1'b0, angle[14:0]}),
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.data_b (16'hc90f),
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.data_p (data_sine_s1_s),
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.ddata_in ({ddata_in, angle[15]}),
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.ddata_out ({ddata_s1_s, data_msb_s1_s}));
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// level 1, (final) B*x;
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ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2_i (
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.clk (clk),
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.data_a (data_sine_s1_s[30:15]),
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.data_b (16'h19f0),
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.data_p (data_sine_s2_i_s),
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.ddata_in ({ddata_s1_s, data_msb_s1_s, data_sine_s1_s[30:15]}),
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.ddata_out ({ddata_s2_i_s, data_msb_s2_i_s, data_delay_s2_i_s}));
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// level 2 inputs, B*x and (1-A*x)
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always @(posedge clk) begin
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ddata_s2_i <= ddata_s2_i_s;
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data_msb_s2_i <= data_msb_s2_i_s;
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data_delay_s2_i <= data_delay_s2_i_s;
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data_sine_s2_i <= 16'ha2f9 - data_sine_s2_i_s[28:13];
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end
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// level 2, second order (A*x2 + B*x)
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ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s2 (
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.clk (clk),
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.data_a (data_delay_s2_i),
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.data_b (data_sine_s2_i),
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.data_p (data_sine_s2_s),
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.ddata_in ({ddata_s2_i, data_msb_s2_i}),
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.ddata_out ({ddata_s2_s, data_msb_s2_s}));
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always @(posedge clk) begin
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ddata_s2 <= ddata_s2_s;
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data_msb_s2 <= data_msb_s2_s;
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if (data_sine_s2_s[31:29] == 0) begin
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data_sine_s2 <= data_sine_s2_s[28:13];
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end else begin
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data_sine_s2 <= 16'hffff;
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end
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end
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// level 2, intermediate (B*y)
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ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s3_i (
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.clk (clk),
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.data_a (data_sine_s2),
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.data_b (16'h3999),
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.data_p (data_sine_s3_i_s),
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.ddata_in ({ddata_s2, data_msb_s2, data_sine_s2}),
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.ddata_out ({ddata_s3_i_s, data_msb_s3_i_s, data_delay_s3_i_s}));
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always @(posedge clk) begin
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ddata_s3_i <= ddata_s3_i_s;
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data_msb_s3_i <= data_msb_s3_i_s;
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data_delay_s3_i <= data_delay_s3_i_s;
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data_sine_s3_i <= 16'hc666 + data_sine_s3_i_s[31:16];
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end
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// level 2, second order (A*y2 + B*y)
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ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s3 (
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.clk (clk),
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.data_a (data_delay_s3_i),
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.data_b (data_sine_s3_i),
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.data_p (data_sine_s3_s),
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.ddata_in ({ddata_s3_i, data_msb_s3_i}),
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.ddata_out ({ddata_s3_s, data_msb_s3_s}));
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always @(posedge clk) begin
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ddata_s4 <= ddata_s3_s;
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data_msb <= data_msb_s3_s;
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data_sine_p <= data_sine_s3_s[31:17];
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data_sine_n <= ~data_sine_s3_s[31:17] + 1'b1;
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ddata_out <= ddata_s4;
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sine <= (data_msb == 1'b1) ? {1'b1, data_sine_n} : {1'b0, data_sine_p};
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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