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Istvan Csomortani 2e4640d5c5 ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl 2014-12-09 16:17:46 +02:00
library plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width 2014-12-09 13:59:19 +02:00
projects ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl 2014-12-09 16:17:46 +02:00
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README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga