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Lars-Peter Clausen 2e173201d4 daq2: daq2_qsys.tcl: Use sys_dma_clk 
Use the sys_dma_clk clock module for clock and reset signals of the data
path, rather than using the A10GX specific sys_ddr3_cntrl signals. This
enables compatibility for all Altera/Intel platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-07-17 17:38:20 +02:00
library jesd204: tx_ctrl: Fix status_sync assignment 2017-07-17 17:13:02 +02:00
projects daq2: daq2_qsys.tcl: Use sys_dma_clk 2017-07-17 17:38:20 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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