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ad_addsub.v
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…
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ad_adl5904_rst.v
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…
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ad_axis_inf_rx.v
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…
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ad_b2g.v
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…
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ad_csc.v
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ad_csc: Generalize for CrYCB 2 RGB conversion
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2019-02-12 10:43:46 +02:00 |
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ad_csc_CrYCb2RGB.v
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ad_csc: Generalize for CrYCB 2 RGB conversion
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2019-02-12 10:43:46 +02:00 |
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ad_csc_RGB2CrYCb.v
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ad_csc(RGB2CrYCb): use signed multiplication.
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2019-02-12 10:43:46 +02:00 |
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ad_datafmt.v
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ad_datafmt: Fix Quartus warnings
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2018-04-13 11:32:57 +02:00 |
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ad_dds.v
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ad_dds: Fix synthesis updates
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2018-07-18 18:19:30 +03:00 |
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ad_dds_1.v
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ad_dds: Add selectable phase width option.
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2018-07-18 18:19:30 +03:00 |
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ad_dds_2.v
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ad_dds_2: Don't try to round if signal is not truncated
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2018-08-28 10:08:22 +02:00 |
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ad_dds_cordic_pipe.v
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ad_dds: Separated phase width from data width
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2018-07-18 18:19:30 +03:00 |
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ad_dds_sine.v
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…
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ad_dds_sine_cordic.v
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ad_dds: Fix synthesis updates
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2018-07-18 18:19:30 +03:00 |
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ad_edge_detect.v
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…
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ad_g2b.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_iqcor.v
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…
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ad_mem.v
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util_axis_fifo: instantiate block ram in async mode
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2018-04-11 15:09:54 +03:00 |
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ad_mem_asym.v
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ad_mem_asym: Improve the implementation of the asymmetric RAM
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2018-08-06 17:29:05 +03:00 |
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ad_perfect_shuffle.v
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library: Add perfect shuffle module
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2018-10-15 15:34:31 +03:00 |
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ad_pnmon.v
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…
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ad_pps_receiver.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_pps_receiver_constr.ttcl
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axi_ad9361: Update constraint file
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2017-08-04 16:20:33 +01:00 |
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ad_rst.v
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ad_rst: Synthesis attribute 'preserve' is redundant
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2018-08-14 17:54:14 +03:00 |
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ad_ss_422to444.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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ad_ss_444to422.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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ad_sysref_gen.v
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ad_sysref_gen: Fix quartus warnings
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2018-04-13 11:32:57 +02:00 |
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ad_tdd_control.v
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ad_tdd_control: Register tdd_endof_frame
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2018-08-10 14:06:38 +03:00 |
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ad_xcvr_rx_if.v
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common/ad_xcvr_rx_if: make core more generic
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2018-12-04 14:02:22 +02:00 |
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axi_ctrlif.vhd
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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axi_streaming_dma_rx_fifo.vhd
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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axi_streaming_dma_tx_fifo.vhd
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…
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dma_fifo.vhd
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…
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pl330_dma_fifo.vhd
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…
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up_adc_channel.v
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…
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up_adc_common.v
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up_adc_common/up_dac_common: reduce address space to half
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2019-01-23 17:44:33 +02:00 |
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up_axi.v
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…
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up_clkgen.v
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ad_rst: Update all the modules, which instantiate the ad_rst
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2018-08-06 21:24:41 +03:00 |
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up_clock_mon.v
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…
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up_dac_channel.v
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…
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up_dac_common.v
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up_dac_common: fix address decoding
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2019-02-19 15:38:45 +02:00 |
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up_delay_cntrl.v
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ad_rst: Update all the modules, which instantiate the ad_rst
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2018-08-06 21:24:41 +03:00 |
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up_hdmi_rx.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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up_hdmi_tx.v
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ad_rst: Update all the modules, which instantiate the ad_rst
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2018-08-06 21:24:41 +03:00 |
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up_pmod.v
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ad_rst: Update all the modules, which instantiate the ad_rst
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2018-08-06 21:24:41 +03:00 |
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up_tdd_cntrl.v
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…
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up_xfer_cntrl.v
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…
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up_xfer_status.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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util_axis_upscale.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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util_delay.v
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…
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util_pulse_gen.v
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util_pulse_gen: Add an input configuration port for pulse width attribute
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2019-03-19 16:33:10 +00:00 |
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