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Lars-Peter Clausen f98c9e439b ad_dds_2: Don't try to round if signal is not truncated 
If DDS_DW is equal to DDS_D_DW there is no signal truncation and
consequentially no rounding should be performed. But the check whether
rounding should be performed currently is for if DDS_DW is less or equal to
DDS_D_DW.

When both are equal C_T_WIDTH is 0. This results in the expression
'{(C_T_WIDTH){dds_data_int[DDS_D_DW-1]}};' being a 0 width signal. This is
not legal Verilog, but both the Intel and Xilinx tools seem to accept it
nevertheless.

But the iverilog simulation tools generates the following error:

	ad_dds_2.v:102: error: Concatenation repeat may not be zero in this context.

Xilinx Vivado also generates the following warning:

	WARNING: [Synth 8-693] zero replication count - replication ignored [ad_dds_2.v:102]

Change the condition so that truncation is only performed when DDS_DW is
less than DDS_D_DW. This fixes both the error and the warning.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-08-28 10:08:22 +02:00
..
ad_addsub.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_adl5904_rst.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_axis_inf_rx.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_b2g.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_1.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_1_add.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_1_mul.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_CrYCb2RGB.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_RGB2CrYCb.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_datafmt.v ad_datafmt: Fix Quartus warnings 2018-04-13 11:32:57 +02:00
ad_dds.v ad_dds: Fix synthesis updates 2018-07-18 18:19:30 +03:00
ad_dds_1.v ad_dds: Add selectable phase width option. 2018-07-18 18:19:30 +03:00
ad_dds_2.v ad_dds_2: Don't try to round if signal is not truncated 2018-08-28 10:08:22 +02:00
ad_dds_cordic_pipe.v ad_dds: Separated phase width from data width 2018-07-18 18:19:30 +03:00
ad_dds_sine.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_dds_sine_cordic.v ad_dds: Fix synthesis updates 2018-07-18 18:19:30 +03:00
ad_edge_detect.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_g2b.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_iqcor.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_mem.v util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
ad_mem_asym.v ad_mem_asym: Improve the implementation of the asymmetric RAM 2018-08-06 17:29:05 +03:00
ad_pnmon.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_pps_receiver.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_pps_receiver_constr.ttcl axi_ad9361: Update constraint file 2017-08-04 16:20:33 +01:00
ad_rst.v ad_rst: Synthesis attribute 'preserve' is redundant 2018-08-14 17:54:14 +03:00
ad_ss_422to444.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_ss_444to422.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_sysref_gen.v ad_sysref_gen: Fix quartus warnings 2018-04-13 11:32:57 +02:00
ad_tdd_control.v ad_tdd_control: Register tdd_endof_frame 2018-08-10 14:06:38 +03:00
ad_xcvr_rx_if.v ad_xcvr_rx_if: rx_ip_sof_d register has a width of 4 bits 2018-04-11 15:09:54 +03:00
axi_ctrlif.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_streaming_dma_rx_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_streaming_dma_tx_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
dma_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
pl330_dma_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_adc_channel.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_adc_common.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_axi.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_clkgen.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_clock_mon.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_dac_channel.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_dac_common.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_delay_cntrl.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_hdmi_rx.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_hdmi_tx.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_pmod.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_tdd_cntrl.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_xfer_cntrl.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_xfer_status.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_axis_upscale.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_delay.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_pulse_gen.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00