387 lines
13 KiB
Verilog
Executable File
387 lines
13 KiB
Verilog
Executable File
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module frame_align_tb;
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parameter VCD_FILE = "frame_align_tb.vcd";
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parameter NUM_LANES = 4;
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parameter NUM_LINKS = 1;
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parameter OCTETS_PER_FRAME = 4;
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parameter FRAMES_PER_MULTIFRAME = 16;
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parameter ENABLE_SCRAMBLER = 1;
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parameter BUFFER_EARLY_RELEASE = 1;
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parameter LANE_DELAY = 1;
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parameter ALIGN_ERROR_PERCENT = 50;
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localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 4;
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localparam TX_LATENCY = 3;
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localparam RX_LATENCY = 3;
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localparam BASE_LATENCY = TX_LATENCY + RX_LATENCY;
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`define TIMEOUT 1000000
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`include "tb_base.v"
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reg [5:0] tx_counter = 'h00;
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reg [5:0] rx_counter = 'h00;
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reg [NUM_LANES*32-1:0] rx_mask = 'hffff0000;
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wire tx_ready;
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wire rx_valid;
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wire [NUM_LANES*32-1:0] rx_data;
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reg data_mismatch = 1'b1;
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wire [NUM_LINKS-1:0] sync;
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always @(posedge clk) begin
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if (sync == 1'b0) begin
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tx_counter <= 'h00000000;
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end else if (tx_ready == 1'b1) begin
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tx_counter <= tx_counter + 1'b1;
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end
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end
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always @(posedge clk) begin
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if (sync == 1'b0) begin
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rx_counter <= 'h00000000;
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if (ENABLE_SCRAMBLER == 1'b1) begin
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rx_mask <= {NUM_LANES{32'hffff0000}}; // First two octets are invalid due to scrambling
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end else begin
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rx_mask <= {NUM_LANES{32'hffffffff}};
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end
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end else if (rx_valid == 1'b1) begin
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rx_counter <= rx_counter + 1'b1;
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rx_mask <= {NUM_LANES{32'hffffffff}};
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end
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end
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wire [31:0] tx_data = {tx_counter,2'h3,tx_counter,2'h2,tx_counter,2'h1,tx_counter,2'h0};
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wire [31:0] rx_ref_data = {rx_counter,2'h3,rx_counter,2'h2,rx_counter,2'h1,rx_counter,2'h0};
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wire [NUM_LANES*32-1:0] phy_data_out;
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wire [NUM_LANES*4-1:0] phy_charisk_out;
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wire [NUM_LANES*32-1:0] phy_data_delayed;
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wire [NUM_LANES*4-1:0] phy_charisk_delayed;
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reg [NUM_LANES*32-1:0] phy_data_in;
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reg [NUM_LANES*4-1:0] phy_charisk_in;
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reg align_err_mf;
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reg align_err_f;
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reg cur_err;
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reg [5:0] sysref_counter = 'h00;
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reg sysref_rx = 1'b0;
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reg sysref_tx = 1'b0;
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always @(posedge clk) begin
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if (sysref_counter == 'h2f)
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sysref_rx <= ~sysref_rx;
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sysref_counter <= sysref_counter + 1'b1;
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sysref_tx <= sysref_rx;
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end
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localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES;
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reg [10:0] phy_delay_fifo_wr;
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reg [36*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1];
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always @(posedge clk) begin
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phy_delay_fifo[phy_delay_fifo_wr] <= {phy_charisk_out,phy_data_out};
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if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin
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phy_delay_fifo_wr <= 'h00;
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end else begin
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phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1;
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end
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end
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initial begin
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align_err_mf = 1'b0;
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align_err_f = 1'b0;
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#100000;
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align_err_f = 1'b1;
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#50000;
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align_err_f = 1'b0;
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#100000;
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align_err_mf = 1'b1;
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#50000;
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align_err_mf = 1'b0;
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#100000;
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align_err_f = 1'b1;
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align_err_mf = 1'b1;
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#50000;
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align_err_f = 1'b0;
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align_err_mf = 1'b0;
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#100000;
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end
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always @(posedge clk) begin
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if(ALIGN_ERROR_PERCENT != 0) begin
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cur_err <= $urandom_range(99) < ALIGN_ERROR_PERCENT;
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end else begin
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cur_err <= 1'b0;
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end
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end
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genvar i;
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generate for (i = 0; i < NUM_LANES; i = i + 1) begin
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localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY);
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assign phy_data_delayed[32*i+31:32*i] =
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phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][32*i+31:32*i];
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assign phy_charisk_delayed[4*i+3:4*i] =
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phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][4*i+3+NUM_LANES*32:4*i+32*NUM_LANES];
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end endgenerate
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always @(*) begin
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phy_data_in = phy_data_delayed;
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phy_charisk_in = phy_charisk_delayed;
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if(cur_err) begin
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if(align_err_mf) begin
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phy_data_in = {NUM_LANES*4{8'h7C}};
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phy_charisk_in = {NUM_LANES*4{1'b1}};
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end else if(align_err_f) begin
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phy_data_in = {NUM_LANES*4{8'hFC}};
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phy_charisk_in = {NUM_LANES*4{1'b1}};
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end
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end
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end
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wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
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wire [NUM_LINKS-1:0] tx_cfg_links_disable;
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wire [7:0] tx_cfg_beats_per_multiframe;
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wire [7:0] tx_cfg_octets_per_frame;
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wire [7:0] tx_cfg_lmfc_offset;
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wire tx_cfg_sysref_disable;
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wire tx_cfg_sysref_oneshot;
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wire tx_cfg_continuous_cgs;
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wire tx_cfg_continuous_ilas;
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wire tx_cfg_skip_ilas;
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wire [7:0] tx_cfg_mframes_per_ilas;
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wire tx_cfg_disable_char_replacement;
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wire tx_cfg_disable_scrambler;
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wire tx_ilas_config_rd;
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wire [1:0] tx_ilas_config_addr;
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wire [32*NUM_LANES-1:0] tx_ilas_config_data;
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jesd204_tx_static_config #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
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.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
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.SCR(ENABLE_SCRAMBLER)
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) i_tx_cfg (
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.clk(clk),
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.cfg_lanes_disable(tx_cfg_lanes_disable),
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.cfg_links_disable(tx_cfg_links_disable),
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.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
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.cfg_octets_per_frame(tx_cfg_octets_per_frame),
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.cfg_lmfc_offset(tx_cfg_lmfc_offset),
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.cfg_sysref_disable(tx_cfg_sysref_disable),
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.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
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.cfg_continuous_cgs(tx_cfg_continuous_cgs),
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.cfg_continuous_ilas(tx_cfg_continuous_ilas),
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.cfg_skip_ilas(tx_cfg_skip_ilas),
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.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
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.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
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.cfg_disable_scrambler(tx_cfg_disable_scrambler),
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.ilas_config_rd(tx_ilas_config_rd),
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.ilas_config_addr(tx_ilas_config_addr),
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.ilas_config_data(tx_ilas_config_data)
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);
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jesd204_tx #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS)
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) i_tx (
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.clk(clk),
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.reset(reset),
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.cfg_lanes_disable(tx_cfg_lanes_disable),
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.cfg_links_disable(tx_cfg_links_disable),
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.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
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.cfg_octets_per_frame(tx_cfg_octets_per_frame),
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.cfg_lmfc_offset(tx_cfg_lmfc_offset),
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.cfg_sysref_disable(tx_cfg_sysref_disable),
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.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
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.cfg_continuous_cgs(tx_cfg_continuous_cgs),
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.cfg_continuous_ilas(tx_cfg_continuous_ilas),
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.cfg_skip_ilas(tx_cfg_skip_ilas),
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.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
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.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
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.cfg_disable_scrambler(tx_cfg_disable_scrambler),
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.ilas_config_rd(tx_ilas_config_rd),
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.ilas_config_addr(tx_ilas_config_addr),
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.ilas_config_data(tx_ilas_config_data),
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.ctrl_manual_sync_request(1'b0),
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.tx_ready(tx_ready),
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.tx_data({NUM_LANES{tx_data}}),
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.sync(sync),
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.sysref(sysref_tx),
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.phy_data(phy_data_out),
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.phy_charisk(phy_charisk_out)
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);
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wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
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wire [NUM_LINKS-1:0] rx_cfg_links_disable;
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wire [7:0] rx_cfg_beats_per_multiframe;
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wire [7:0] rx_cfg_octets_per_frame;
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wire [7:0] rx_cfg_lmfc_offset;
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wire rx_sysref_disable;
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wire rx_sysref_oneshot;
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wire rx_cfg_disable_scrambler;
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wire rx_cfg_disable_char_replacement;
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wire rx_cfg_buffer_early_release;
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wire [7:0] rx_cfg_buffer_delay;
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wire [NUM_LANES-1:0] rx_status_lane_ifs_ready;
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wire [NUM_LANES*14-1:0] rx_status_lane_latency;
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wire [NUM_LANES*8-1:0] rx_status_lane_frame_align_err_cnt;
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wire [7:0] rx_cfg_frame_align_err_threshold;
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jesd204_rx_static_config #(
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.NUM_LANES(NUM_LANES),
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.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
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.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
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.SCR(ENABLE_SCRAMBLER),
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.BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE)
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) i_rx_cfg (
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.clk(clk),
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.cfg_lanes_disable(rx_cfg_lanes_disable),
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.cfg_links_disable(rx_cfg_links_disable),
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.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
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.cfg_octets_per_frame(rx_cfg_octets_per_frame),
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.cfg_lmfc_offset(rx_cfg_lmfc_offset),
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.cfg_sysref_disable(rx_cfg_sysref_disable),
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.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
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.cfg_disable_scrambler(rx_cfg_disable_scrambler),
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.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
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.cfg_buffer_delay(rx_cfg_buffer_delay),
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.cfg_buffer_early_release(rx_cfg_buffer_early_release),
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.cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold)
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);
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jesd204_rx #(
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.NUM_LANES(NUM_LANES),
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.ENABLE_FRAME_ALIGN_CHECK(1),
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.ENABLE_FRAME_ALIGN_ERR_RESET(1)
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) i_rx (
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.clk(clk),
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.reset(reset),
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.cfg_lanes_disable(rx_cfg_lanes_disable),
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.cfg_links_disable(rx_cfg_links_disable),
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.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
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.cfg_octets_per_frame(rx_cfg_octets_per_frame),
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.cfg_lmfc_offset(rx_cfg_lmfc_offset),
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.cfg_sysref_disable(rx_cfg_sysref_disable),
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.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
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.cfg_disable_scrambler(rx_cfg_disable_scrambler),
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.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
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.cfg_buffer_delay(rx_cfg_buffer_delay),
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.cfg_buffer_early_release(rx_cfg_buffer_early_release),
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.cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold),
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.sync(sync),
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.sysref(sysref_rx),
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.rx_data(rx_data),
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.rx_valid(rx_valid),
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.phy_data(phy_data_in),
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.phy_charisk(phy_charisk_in),
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.phy_notintable({NUM_LANES{4'b0000}}),
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.phy_disperr({NUM_LANES{4'b0000}}),
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.status_lane_ifs_ready(rx_status_lane_ifs_ready),
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.status_lane_latency(rx_status_lane_latency),
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.status_lane_frame_align_err_cnt(rx_status_lane_frame_align_err_cnt)
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);
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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data_mismatch <= 1'b0;
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end else if (rx_valid == 1'b1) begin
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if ((rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask)) begin
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data_mismatch <= 1'b1;
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end
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end
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end
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reg [NUM_LANES-1:0] lane_latency_match;
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generate for (i = 0; i < NUM_LANES; i = i + 1) begin
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localparam LANE_OFFSET = BASE_LATENCY + LANE_DELAY + BEATS_PER_MULTIFRAME + i;
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always @(posedge clk) begin
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if (rx_status_lane_ifs_ready[i] == 1'b1 &&
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rx_status_lane_latency[i*14+13:i*14+2] == LANE_OFFSET) begin
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lane_latency_match[i] <= 1'b1;
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end else begin
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lane_latency_match[i] <= 1'b0;
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end
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end
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end endgenerate
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always @(*) begin
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if (rx_valid !== 1'b1 || tx_ready !== 1'b1 || data_mismatch == 1'b1 ||
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&lane_latency_match != 1'b1) begin
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failed <= 1'b1;
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end else begin
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failed <= 1'b0;
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end
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end
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endmodule
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