280 lines
8.6 KiB
Verilog
280 lines
8.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_response_manager #(
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter BYTES_PER_BURST_WIDTH = 7,
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parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8),
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parameter ASYNC_CLK_DEST_REQ = 1
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)(
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// Interface to destination side
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input dest_clk,
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input dest_resetn,
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input dest_response_valid,
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output dest_response_ready,
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input [1:0] dest_response_resp,
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input dest_response_partial,
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input dest_response_resp_eot,
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input [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length,
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// Interface to processor
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input req_clk,
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input req_resetn,
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output response_eot,
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output reg [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length = 'h0,
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output response_partial,
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output reg response_valid = 1'b0,
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input response_ready,
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// Interface to requester side
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input completion_req_valid,
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input completion_req_last,
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input [1:0] completion_transfer_id
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);
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localparam STATE_IDLE = 3'h0;
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localparam STATE_ACC = 3'h1;
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localparam STATE_WRITE_RESPR = 3'h2;
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localparam STATE_ZERO_COMPL = 3'h3;
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localparam STATE_WRITE_ZRCMPL = 3'h4;
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reg [2:0] state = STATE_IDLE;
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reg [2:0] nx_state;
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localparam DEST_SRC_RATIO = DMA_DATA_WIDTH_DEST/DMA_DATA_WIDTH_SRC;
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localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 :
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DEST_SRC_RATIO > 32 ? 6 :
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DEST_SRC_RATIO > 16 ? 5 :
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DEST_SRC_RATIO > 8 ? 4 :
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DEST_SRC_RATIO > 4 ? 3 :
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DEST_SRC_RATIO > 2 ? 2 :
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DEST_SRC_RATIO > 1 ? 1 : 0;
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localparam BYTES_PER_BEAT_WIDTH = DEST_SRC_RATIO_WIDTH + BYTES_PER_BEAT_WIDTH_SRC;
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localparam BURST_LEN_WIDTH = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH;
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wire do_acc_st;
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wire do_compl;
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reg req_eot = 1'b0;
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reg req_response_partial = 1'b0;
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reg [BYTES_PER_BURST_WIDTH-1:0] req_response_dest_data_burst_length = 'h0;
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wire response_dest_valid;
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reg response_dest_ready = 1'b1;
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wire [1:0] response_dest_resp;
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wire response_dest_resp_eot;
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wire [BYTES_PER_BURST_WIDTH-1:0] response_dest_data_burst_length;
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wire [BURST_LEN_WIDTH-1:0] burst_lenght;
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reg [BURST_LEN_WIDTH-1:0] burst_pointer_end;
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reg [1:0] to_complete_count = 'h0;
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reg [1:0] transfer_id = 'h0;
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reg completion_req_last_found = 1'b0;
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util_axis_fifo #(
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.DATA_WIDTH(BYTES_PER_BURST_WIDTH+1+1),
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.ADDRESS_WIDTH(0),
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.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
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) i_dest_response_fifo (
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.s_axis_aclk(dest_clk),
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.s_axis_aresetn(dest_resetn),
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.s_axis_valid(dest_response_valid),
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.s_axis_ready(dest_response_ready),
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.s_axis_empty(),
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.s_axis_data({dest_response_data_burst_length,
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dest_response_partial,
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dest_response_resp_eot}),
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.s_axis_room(),
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.m_axis_aclk(req_clk),
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.m_axis_aresetn(req_resetn),
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.m_axis_valid(response_dest_valid),
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.m_axis_ready(response_dest_ready),
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.m_axis_data({response_dest_data_burst_length,
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response_dest_partial,
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response_dest_resp_eot}),
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.m_axis_level()
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);
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always @(posedge req_clk)
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begin
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if (response_dest_valid & response_dest_ready) begin
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req_eot <= response_dest_resp_eot;
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req_response_partial <= response_dest_partial;
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req_response_dest_data_burst_length <= response_dest_data_burst_length;
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end
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end
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always @(posedge req_clk)
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begin
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if (req_resetn == 1'b0) begin
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response_dest_ready <= 1'b1;
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end else begin
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response_dest_ready <= (nx_state == STATE_IDLE);
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end
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end
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assign response_eot = (state == STATE_WRITE_RESPR) ? req_eot : 1'b1;
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assign response_partial = (state == STATE_WRITE_RESPR) ? req_response_partial : 1'b0;
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always @(posedge req_clk)
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begin
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if (req_resetn == 1'b0) begin
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response_valid <= 1'b0;
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end else begin
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if (nx_state == STATE_WRITE_RESPR || nx_state == STATE_WRITE_ZRCMPL) begin
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response_valid <= 1'b1;
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end else if (response_ready == 1'b1) begin
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response_valid <= 1'b0;
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end
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end
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end
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// transform the free running pointer from burst memory into burst length
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assign burst_lenght = req_response_dest_data_burst_length[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH] -
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burst_pointer_end - 1'b1;
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always @(posedge req_clk)
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begin
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if (req_resetn == 1'b0) begin
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burst_pointer_end <= {BURST_LEN_WIDTH{1'b1}};
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end else if (state == STATE_ACC) begin
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burst_pointer_end <= req_response_dest_data_burst_length[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH];
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end
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end
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always @(posedge req_clk)
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begin
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if (state == STATE_ZERO_COMPL) begin
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measured_burst_length <= {BYTES_PER_BURST_WIDTH{1'b1}};
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end else if (state == STATE_ACC) begin
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measured_burst_length[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH] <= burst_lenght;
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measured_burst_length[BYTES_PER_BEAT_WIDTH-1 : 0] <=
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req_response_dest_data_burst_length[BYTES_PER_BEAT_WIDTH-1: 0];
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end
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end
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always @(*) begin
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nx_state = state;
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case (state)
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STATE_IDLE: begin
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if (response_dest_valid == 1'b1) begin
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nx_state = STATE_ACC;
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end else if (|to_complete_count) begin
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if (transfer_id == completion_transfer_id)
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nx_state = STATE_ZERO_COMPL;
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end
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end
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STATE_ACC: begin
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nx_state = STATE_WRITE_RESPR;
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end
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STATE_WRITE_RESPR: begin
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if (response_ready == 1'b1) begin
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nx_state = STATE_IDLE;
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end
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end
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STATE_ZERO_COMPL: begin
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if (|to_complete_count) begin
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nx_state = STATE_WRITE_ZRCMPL;
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end else begin
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if (completion_req_last_found == 1'b1) begin
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nx_state = STATE_IDLE;
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end
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end
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end
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STATE_WRITE_ZRCMPL:begin
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if (response_ready == 1'b1) begin
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nx_state = STATE_ZERO_COMPL;
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end
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end
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default: begin
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nx_state = STATE_IDLE;
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end
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endcase
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end
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always @(posedge req_clk) begin
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if (req_resetn == 1'b0) begin
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state <= STATE_IDLE;
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end else begin
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state <= nx_state;
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end
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end
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assign do_compl = (state == STATE_WRITE_ZRCMPL) && response_ready;
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// Once the last completion request from request generator is received
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// we can wait for completions from the destination side
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always @(posedge req_clk) begin
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if (req_resetn == 1'b0) begin
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completion_req_last_found <= 1'b0;
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end else if (completion_req_valid) begin
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completion_req_last_found <= completion_req_last;
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end else if (state ==STATE_ZERO_COMPL && ~(|to_complete_count)) begin
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completion_req_last_found <= 1'b0;
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end
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end
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// Track transfers so we can tell when did the destination completed all its
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// transfers
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always @(posedge req_clk) begin
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if (req_resetn == 1'b0) begin
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transfer_id <= 'h0;
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end else if ((state == STATE_ACC && req_eot) || do_compl) begin
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transfer_id <= transfer_id + 1;
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end
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end
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// Count how many transfers we need to complete
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always @(posedge req_clk) begin
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if (req_resetn == 1'b0) begin
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to_complete_count <= 'h0;
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end else if (completion_req_valid & ~do_compl) begin
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to_complete_count <= to_complete_count + 1;
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end else if (~completion_req_valid & do_compl) begin
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to_complete_count <= to_complete_count - 1;
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end
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end
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endmodule
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