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Lars-Peter Clausen 0a30cdbf99 Add util_cpack2 core 
The util_cpack2 core is similar to the util_upack core. It packs, or
interleaves, a data from multiple ports into a single data. Ports can
optionally be enabled or disabled.

On the input side the cpack2 core uses a multi-port FIFO interface. There
is a single data write signal (fifo_wr_en) for all ports. But each port can
be individually enabled or disabled using the enable signals.

On the output side the cpack2 core uses a single port FIFO interface. When
data is available on the output interface the data write signal
(packed_fifo_wr_en). Data on the packed_fifo_wr_data signal is only valid
when packed_fifo_wr_en is asserted. At other times the content is
undefined. The cpack2 core offers no back-pressure. If data is not consumed
when it is made available it will be lost.

Data from the input ports is accumulated inside the cpack2 core and if
enough data is available to produce a full output vector the data is
forwarded.

This core is build using the common pack infrastructure. The core that is
specific to the cpack2 core is mainly only responsible for generating the
control signals for the external interfaces.

The core is accompanied by a test bench that verifies correct behavior for
all possible combinations of enable masks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-11-28 11:33:11 +02:00
..
altera Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_ad5766 Remove unused DMA overflow signal from DAC DMA interfaces 2018-05-02 17:21:20 +02:00
axi_ad6676 axi_ad6676: Support multiple lane configuration 2018-10-05 15:19:17 +03:00
axi_ad7616 Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_ad9122 axi_ad9122: Increase dds quality 2018-07-18 18:19:30 +03:00
axi_ad9144 ad_ip_jesd204_tpl_dac: Use perfect shuffle helper module 2018-10-15 15:34:31 +03:00
axi_ad9152 ad_ip_jesd204_tpl_dac: Use perfect shuffle helper module 2018-10-15 15:34:31 +03:00
axi_ad9162 axi_ad9162: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
axi_ad9250 axi_ad9250: Use the generic JESD204 ADC receiver core 2018-05-02 17:21:20 +02:00
axi_ad9265 Remove unused DMA underflow signal from ADC DMA interface 2018-05-02 17:21:20 +02:00
axi_ad9361 axi_ad9361: Mark rst output as active high 2018-10-16 15:14:53 +03:00
axi_ad9371 all: Drive undriven input signals, complete interface 2018-08-10 17:00:11 +03:00
axi_ad9434 Remove unused DMA underflow signal from ADC DMA interface 2018-05-02 17:21:20 +02:00
axi_ad9467 Remove unused DMA underflow signal from ADC DMA interface 2018-05-02 17:21:20 +02:00
axi_ad9625 Remove unused DMA underflow signal from ADC DMA interface 2018-05-02 17:21:20 +02:00
axi_ad9671 Remove unused DMA underflow signal from ADC DMA interface 2018-05-02 17:21:20 +02:00
axi_ad9680 axi_ad9680: Use the generic JESD204 ADC receiver core 2018-05-02 17:21:20 +02:00
axi_ad9684 Remove unused DMA underflow signal from ADC DMA interface 2018-05-02 17:21:20 +02:00
axi_ad9739a axi_ad9739a: Use polynomial DDS 2018-07-18 18:19:30 +03:00
axi_ad9963 axi_ad9963: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
axi_adc_decimate Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_adc_trigger Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_adrv9009 axi_adrv9009: Split DATAPATH parameter in multiple parameters for Intel IP 2018-11-27 15:31:21 +02:00
axi_clkgen Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dac_interpolate Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_dmac axi_dmac/tb: Add support for xsim 2018-11-07 12:13:06 +02:00
axi_fmcadc5_sync Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_generic_adc Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_gpreg axi_gpreg: Use the common ad_rst constraints 2018-08-06 21:24:41 +03:00
axi_hdmi_rx Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_hdmi_tx Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_i2s_adi adi_ip: Use 'associate_bus_interface' command to setup the clock and reset for s_axi 2018-08-06 10:14:48 +03:00
axi_intr_monitor Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_logic_analyzer ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
axi_mc_controller Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_mc_current_monitor all: Drive undriven input signals, complete interface 2018-08-10 17:00:11 +03:00
axi_mc_speed all: Drive undriven input signals, complete interface 2018-08-10 17:00:11 +03:00
axi_rd_wr_combiner Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_spdif_rx axi_spdif_rx: clear warning 2018-08-10 17:00:11 +03:00
axi_spdif_tx adi_ip: Use 'associate_bus_interface' command to setup the clock and reset for s_axi 2018-08-06 10:14:48 +03:00
axi_usb_fx3 Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
cn0363 Add missing timescale annotations 2018-10-17 10:32:47 +03:00
common Add missing timescale annotations 2018-10-17 10:32:47 +03:00
cordic_demod Add missing timescale annotations 2018-10-17 10:32:47 +03:00
interfaces axi|util_adxcvr: Expose TX configurable driver ports 2018-10-04 14:37:02 +03:00
jesd204 Add missing timescale annotations 2018-10-17 10:32:47 +03:00
scripts adi_ip_alt: ad_ip_create: Use 'description' for the DISPLAY_NAME propery 2018-08-27 11:53:50 +02:00
spi_engine Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_adcfifo util_adcfifo: Synchronize the ad_rst and use it as a synchronous reset 2018-08-21 11:42:48 +03:00
util_axis_fifo Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_axis_resize Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_axis_upscale Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_bsplit library: Remove empty constraint files 2018-04-11 15:09:54 +03:00
util_cdc Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_cic Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_clkdiv Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_cpack library: Remove empty constraint files 2018-04-11 15:09:54 +03:00
util_dacfifo util_dacfifo: Delete unused registers 2018-10-16 10:29:37 +03:00
util_delay Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_extract Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_fir_dec Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_fir_int Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_gmii_to_rgmii Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_i2c_mixer Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_mfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_pack Add util_cpack2 core 2018-11-28 11:33:11 +02:00
util_pulse_gen Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_rfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_sigma_delta_spi Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_tdd_sync Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_upack library: Remove empty constraint files 2018-04-11 15:09:54 +03:00
util_var_fifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_wfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
xilinx axi_adxcvr: Fix typo in initial parameters values 2018-11-16 14:18:33 +02:00
Makefile Add util_cpack2 core 2018-11-28 11:33:11 +02:00