61 lines
1.9 KiB
Verilog
61 lines
1.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module cic_int #(
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parameter DATA_WIDTH = 12,
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parameter STAGE_WIDTH = 1,
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parameter NUM_STAGES = 1
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) (
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input clk,
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input [NUM_STAGES-1:0] ce,
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input [DATA_WIDTH-1:0] data_in,
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output [DATA_WIDTH-1:0] data_out
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);
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reg [DATA_WIDTH-1:0] state = 'h00;
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wire [DATA_WIDTH-1:0] sum;
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wire [DATA_WIDTH-1:0] mask;
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assign data_out = state;
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assign sum = (data_in & mask) + (state & mask);
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generate
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genvar i;
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for (i = 0; i < NUM_STAGES; i = i + 1) begin
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localparam j = NUM_STAGES - i - 1;
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localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
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localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);
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assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};
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always @(posedge clk) begin
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if (ce[j] == 1'b1) begin
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state[H:L] <= sum[H:L];
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end
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end
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end
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endgenerate
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endmodule
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