118 lines
3.0 KiB
Verilog
118 lines
3.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module cic_comb #(
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parameter DATA_WIDTH = 32,
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parameter SEQ = 1,
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parameter STAGE_WIDTH = 1,
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parameter NUM_STAGES = 1
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) (
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input clk,
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input ce,
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input [NUM_STAGES-1:0] enable,
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input [DATA_WIDTH-1:0] data_in,
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output [DATA_WIDTH-1:0] data_out
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);
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reg [SEQ-1:0] storage[0:DATA_WIDTH-1];
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reg [DATA_WIDTH-1:0] state = 'h00;
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reg [2:0] counter = 'h00;
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reg active = 1'b0;
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integer x;
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initial begin
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for (x = 0; x < DATA_WIDTH; x = x + 1) begin
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storage[x] = 'h00;
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end
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end
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generate if (SEQ != 1) begin
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always @(posedge clk) begin
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if (ce == 1'b1) begin
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counter <= SEQ-1;
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active <= 1'b1;
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end else if (active == 1'b1) begin
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counter <= counter - 1'b1;
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if (counter == 'h1) begin
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active <= 1'b0;
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end
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end
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end
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end
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endgenerate
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wire [DATA_WIDTH-1:0] mask;
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reg [DATA_WIDTH-1:0] data_in_seq;
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wire [DATA_WIDTH-1:0] storage_out;
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wire [DATA_WIDTH-1:0] diff = (data_in_seq | ~mask) - (storage_out & mask);
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always @(*) begin
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if (ce == 1'b1) begin
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data_in_seq <= data_in;
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end else begin
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data_in_seq <= SEQ != 1 ? state : 'h00;
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end
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end
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generate
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genvar i, j;
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for (j = 0; j < NUM_STAGES; j = j + 1) begin
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localparam k = NUM_STAGES - j - 1;
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localparam H = DATA_WIDTH - STAGE_WIDTH * j - 1;
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localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1);
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assign mask[H:L] = {{H-L{1'b1}},k != 0 ? enable[k] : 1'b1};
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for (i = L; i <= H; i = i + 1) begin: shift_r
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always @(posedge clk) begin
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if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
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if (SEQ > 1) begin
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storage[i] <= {storage[i][SEQ-2:0],data_in_seq[i]};
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end else begin
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storage[i] <= data_in_seq[i];
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end
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end
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end
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assign storage_out[i] = storage[i][SEQ-1];
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end
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always @(posedge clk) begin
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if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
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state[H:L] <= diff[H:L];
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end
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end
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end
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endgenerate
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assign data_out = state;
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endmodule
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