Lars-Peter Clausen 264dbfed35 common: rfsom: Add constraints for the eth1 rx clock ... Add clock rate constraints for the eth1 rx clock, otherwise the tools assume the RX paths are unconstrained and creates a bitstream which violates hold times which causes bit errors on the RX path. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2015-06-03 17:21:43 +02:00
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a5gt	a5gt:common: Added phy reset signal from ethernet in pin assignments	2015-01-23 12:31:41 +02:00
a5gte	a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2	2015-01-23 12:30:16 +02:00
a5soc	a5soc: fmcjesdadc1+hdmi version	2014-08-14 09:05:38 -04:00
a10gx	a10gx- no-ddr	2015-06-01 11:00:01 -04:00
ac701	ac701: common, commit ethernet reset pin	2015-05-11 16:41:28 +03:00
c5soc	projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.	2014-08-27 21:46:23 +03:00
kc705	kc705: Common, fixed address range for the flash. Changed the start address so that it won't interfere with other cores	2015-05-23 00:10:06 +03:00
kcu105	kcu105: ddr mig rbc to rcb	2015-04-23 15:30:48 -04:00
mitx045	projects- drp moved to up-clock domain	2015-06-01 14:57:59 -04:00
rfsom	common: rfsom: Add constraints for the eth1 rx clock	2015-06-03 17:21:43 +02:00
vc707	vc707: common, fixed address range for flash	2015-05-23 00:14:08 +03:00
xilinx	sys_dmafifo: Update the p_sys_dacfifo process	2015-05-11 12:20:47 +03:00
zc702	projects- drp moved to up-clock domain	2015-06-01 14:57:59 -04:00
zc706	projects/daq2- drp moved to up clock	2015-06-01 13:39:26 -04:00
zc706pr	zc706pr - 706 partial reconfiguration	2015-05-04 12:33:28 -04:00
zed	projects- drp moved to up-clock domain	2015-06-01 14:57:59 -04:00