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Lars-Peter Clausen d5a1aa81e8 jesd204: Check lane error count in register map testbench 
Assign a unique value to each lane's error count register and verify that
the correct value is returned for the right lane.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-07-24 15:20:28 +02:00
..
.gitignore Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
axi_jesd204_rx_regmap_tb jesd204: axi_jesd204_rx_regmap_tb: Add missing dependency 2017-08-13 10:28:11 +02:00
axi_jesd204_rx_regmap_tb.v jesd204: Check lane error count in register map testbench 2018-07-24 15:20:28 +02:00
axi_jesd204_tx_regmap_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
axi_jesd204_tx_regmap_tb.v jesd204:version: Increase version number fot TX 2018-05-03 19:37:35 +03:00
loopback_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
loopback_tb.v jesd204: Fix loopback testbench 2018-07-24 15:20:28 +02:00
run_tb.sh Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_cgs_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_cgs_tb.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_ctrl_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_ctrl_tb.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_lane_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_lane_tb.v jesd204: Add RX error statistics (#98) 2018-05-07 15:33:00 +03:00
rx_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_tb.v jesd204: Add RX error statistics (#98) 2018-05-07 15:33:00 +03:00
scrambler_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
scrambler_tb.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
soft_pcs_8b10b_sequence_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_8b10b_sequence_tb.v jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_8b10b_table_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_8b10b_table_tb.v jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_loopback_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_loopback_tb.v jesd204_soft_pcs_loopback_tb: Add parameter for lane polarity inversion 2018-05-02 09:37:23 +02:00
soft_pcs_pattern_align_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_pattern_align_tb.v jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
tb_base.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
tx_ctrl_phase_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
tx_ctrl_phase_tb.v jesd204: tb: Fix signal width mismatch warnings 2017-06-20 17:39:41 +02:00
tx_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
tx_tb.v jesd204:tx_ctrl: Update the sync_request logic 2018-05-03 19:37:35 +03:00