pluto_hdl_adi/library/common
Lars-Peter Clausen 67f204e10e library: Add perfect shuffle module
The perfect shuffle is a common operation in data processing. Add a shared
module that implements this operation.

Having this in a shared module rather than open-coding every instance makes
sure that there are clear and well defined semantics associated with the
operation that are the same each time. This should ease review, maintenance and
understanding of the code.

The perfect shuffle splits the input vector into NUM_GROUPS groups and then
each group in WORDS_PER_GROUP. The output vector consists of
WORDS_PER_GROUP groups and each group has NUM_GROUPS words. The data is
remapped, so that the i-th word of the j-th word in the output vector is
the j-th word of the i-th group of the input vector.

The inverse operation of the perfect shuffle is the perfect shuffle with
both parameters swapped.
I.e. [perfect_suffle B A [perfect_shuffle A B data]] == data

Examples:
  NUM_GROUPS = 2, WORDS_PER_GROUP = 4
    [A B C D a b c d] => [A a B b C c D d]
  NUM_GROUPS = 4, WORDS_PER_GROUP = 2
    [A a B b C c D d] => [A B C D a b c d]
  NUM_GROUPS = 3, WORDS_PER_GROUP = 2
    [A B a b 1 2] => [A a 1 B b 2]

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-15 15:34:31 +03:00
..
ad_addsub.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_adl5904_rst.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_axis_inf_rx.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_b2g.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_1.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_1_add.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_1_mul.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_CrYCb2RGB.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_csc_RGB2CrYCb.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_datafmt.v ad_datafmt: Fix Quartus warnings 2018-04-13 11:32:57 +02:00
ad_dds.v ad_dds: Fix synthesis updates 2018-07-18 18:19:30 +03:00
ad_dds_1.v ad_dds: Add selectable phase width option. 2018-07-18 18:19:30 +03:00
ad_dds_2.v ad_dds_2: Don't try to round if signal is not truncated 2018-08-28 10:08:22 +02:00
ad_dds_cordic_pipe.v ad_dds: Separated phase width from data width 2018-07-18 18:19:30 +03:00
ad_dds_sine.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_dds_sine_cordic.v ad_dds: Fix synthesis updates 2018-07-18 18:19:30 +03:00
ad_edge_detect.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_g2b.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_iqcor.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_mem.v util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
ad_mem_asym.v ad_mem_asym: Improve the implementation of the asymmetric RAM 2018-08-06 17:29:05 +03:00
ad_perfect_shuffle.v library: Add perfect shuffle module 2018-10-15 15:34:31 +03:00
ad_pnmon.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_pps_receiver.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_pps_receiver_constr.ttcl axi_ad9361: Update constraint file 2017-08-04 16:20:33 +01:00
ad_rst.v ad_rst: Synthesis attribute 'preserve' is redundant 2018-08-14 17:54:14 +03:00
ad_ss_422to444.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_ss_444to422.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_sysref_gen.v ad_sysref_gen: Fix quartus warnings 2018-04-13 11:32:57 +02:00
ad_tdd_control.v ad_tdd_control: Register tdd_endof_frame 2018-08-10 14:06:38 +03:00
ad_xcvr_rx_if.v ad_xcvr_rx_if: rx_ip_sof_d register has a width of 4 bits 2018-04-11 15:09:54 +03:00
axi_ctrlif.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_streaming_dma_rx_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_streaming_dma_tx_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
dma_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
pl330_dma_fifo.vhd license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_adc_channel.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_adc_common.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_axi.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_clkgen.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_clock_mon.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_dac_channel.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_dac_common.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_delay_cntrl.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_hdmi_rx.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_hdmi_tx.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_pmod.v ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
up_tdd_cntrl.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_xfer_cntrl.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
up_xfer_status.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_axis_upscale.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_delay.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_pulse_gen.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00