143 lines
5.9 KiB
Markdown
143 lines
5.9 KiB
Markdown
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# AD_FMCLIDAR1_EBZ HDL reference design
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## Overview
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The following design supports both Xilinx and Intel FPGA's. The [AD_FMCLIDAR1_EBZ](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCLIDAR1-EBZ.html)
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prototyping system connects to the FPGA carrier board through a FMC (FPGA Mezzanine Cad)
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high pin count connector.
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Detailed user guide of the prototyping platform can be found [here](https://wiki.analog.com/resources/eval/user-guides/ad-fmclidar1-ebz).
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Currently supported carriers:
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| Carrier name | FMC connector |
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| ------------- | ------------- |
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| ZC706 | FMC_HPC |
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| ZCU102 | HPC0 |
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| Arria10SOC* | FMCA_HPC |
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The design is easily portable to any Xilinx or Intel FPGA carrier board, which
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has an FMC HPC connector, and have all the required connections. (See more info
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in [system_constr.xdc](./zc706/system_constr.xdc) or [system_project.tcl](./a10soc/system_project.tcl))
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You can find a porting guide in the [wiki.analog.com](https://wiki.analog.com/resources/fpga/docs/hdl/porting_project_quick_start_guide).
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### NOTE
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The Arria10SOC carrier requires a hardware rework to function correctly.
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The rework connects FMC_A header pins directly to the FPGA so that they can be
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accessed by the fabric.
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#### Changes required:
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**REMOVE**: R575, R576, R621, R633, R612, R613
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**POPULATE**: R574, R577, R620, R632, R610, R611
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### Directory Structure
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| Directory | Description |
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| --------- | ----------- |
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| common | Common verilog and block design Tcl files |
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| zc706 | ZC706 specific source files |
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| zcu102 | ZCU102 specific source files |
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| a10soc | Arria10SOC specific source files |
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More information about the directory structure of the HDL repository can be found [here](https://wiki.analog.com/resources/fpga/docs/git).
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## Build instructions
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The project is using GNU Make for build and bitstream generation. Change your directory
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to your targeted carrier and run **make**.
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More information about how to build HDL projects can be found [here](http://wiki.analog.com/resources/fpga/docs/build).
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## Architecture
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The main scope of the HDL design is to provide all the required digital interfaces
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for the data acquisition board of the prototyping system.
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The following block diagram presents the simplified system architecture:
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### AXI_LASER_DRIVER IP
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The axi_laser_driver IP is responsible to generate a narrow pulse for the laser
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driver circuit, to control the TIA channel selection on the analog front end (AFE)
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board, and to synchronize the data acquisition to the generated pulses.
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More information about the IP can be found [here](https://wiki.analog.com/resources/fpga/docs/axi_laser_driver).
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### Control interfaces
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| Name | Type | Details |
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| ---- | ---- | ------- |
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| adc_fd* | GPIO | Monitors the AD9094 Fast detect output lines |
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| adc_pwdn | GPIO | Controls the AD9094 Power-Down input line |
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| spi_adc_* | 4-wire SPI | AD9094 configuration interface |
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| spi_vco_* | 3-wire SPI | ADF436-7 configuration interface |
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| spi_clkgen_* | 4-wire SPI | AD9528 configuration interface |
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| laser_driver_p\n | LVDS output | It controls the laser driver circuit, it is generated by the axi_laser_driver IP instance |
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| laser_gpio[13:0] | GPIO | Unused GPIO line on the lase board |
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| tia_chsel[7:0] | CMOS output | TIA channel selection lines, it is controlled by the axi_laser_driver instance |
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| afe_dac_sda\scl\load\clr_n | I2C/GPIO | AD5627 configuration interface |
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| rx_ref_clk_p\n | LVDS | JESD204B reference clock for the high-speed gigabit transceivers; runs at 250MHz |
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| rx_device_clk_p\n | LVDS | JESD204B device clock for the transport layer and additional data processing; runs at 250MHz |
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| rx_data_p\n[3:0] | CML | JESD204B high-speed serial lanes; runs at 10Gbps |
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| rx_sync_p\n[1:0] | LVDS | JESD204B SYNC signals for interface synchronization |
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| rx_sysref_p\n | LVDS | JESD204B SYSREF signal for deterministic latency |
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### JESD204B interface
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The JESD204B interface runs in Subclass 1 mode to ensure the deterministic latency
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of the link. The following tables are summarizing the JESD204B important configuration
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parameter and attributes.
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| Parameter name | Abbreviation |Value |
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| -------------- | ------------ | ---- |
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| Number of lanes | L | 4 |
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| Number of converter | M | 4 |
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| Converter resolution | NP | 8 |
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| Total number of Bits per Sample| NP | 8 |
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| Samples per frame | S | 1 |
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| Octets per frame | F | 1 |
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| Frames per Multiframe | K | 32 |
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| Number of control bits | CS | 0 |
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| Rates and Clocks | Value |
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| ---------------- | ----- |
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| Sample rate | 1GSPS |
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| Lane rate | 10Gbps |
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| GT reference clock | 250MHz |
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| Device clock | 250 MHz |
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## Known issues
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### The Lidar boards do not power up
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**Problem:** The Lidar boards do not power up because the PG_C2M pull-up resistor value on the carrier (Arria 10) is too high.
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**Solution:** On Arria 10 - place a 4k7 ohms resistor in parallel with R5517.
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**Note:**
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1. The PG_C2M can no longer be software controlled. As soon as there is an auxiliary 3V3 on the carrier, the Lidar platform receives the power up command.
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2. This problem only affects Lidar Rev B.
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## Support
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For technical support please visit [FPGA Referece Designs](https://ez.analog.com/fpga/) community in EngineerZone.
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# AD_FMCLIDAR1_EBZ HDL Project
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/AD-FMCLIDAR1-EBZ)
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* Parts : []()
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad-fmclidar1-ebz
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* HDL Doc: https://wiki.analog.com/resources/fpga/docs/hdl
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* Linux Drivers: https://wiki.analog.com/resources/fpga/docs/axi_laser_driver
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