Go to file
Adrian Costina 20a223be99 util_var_fifo: Move BRAM outside of the core so that it can be generated using Xilinx IP 2017-04-18 12:17:40 +02:00
library util_var_fifo: Move BRAM outside of the core so that it can be generated using Xilinx IP 2017-04-18 12:17:40 +02:00
projects m2k: standalone: Rework PS7 clocking 2017-04-18 12:17:40 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects

Branches

Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.

Latest Release Notes

HDL User Guide

HDL Help & Support