133 lines
3.9 KiB
Verilog
133 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_clock_mon (
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// processor interface
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input up_rstn,
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input up_clk,
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output reg [31:0] up_d_count,
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// device interface
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input d_rst,
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input d_clk);
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// internal registers
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reg [15:0] up_count = 'd1;
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reg up_count_run = 'd0;
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reg up_count_running_m1 = 'd0;
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reg up_count_running_m2 = 'd0;
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reg up_count_running_m3 = 'd0;
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reg d_count_run_m1 = 'd0;
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reg d_count_run_m2 = 'd0;
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reg d_count_run_m3 = 'd0;
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reg [32:0] d_count = 'd0;
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// internal signals
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wire up_count_capture_s;
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wire d_count_reset_s;
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// processor reference
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// Capture on the falling edge of running
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assign up_count_capture_s = up_count_running_m3 == 1'b1 && up_count_running_m2 == 1'b0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_count_running_m1 <= 1'b0;
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up_count_running_m2 <= 1'b0;
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up_count_running_m3 <= 1'b0;
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end else begin
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up_count_running_m1 <= d_count_run_m3;
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up_count_running_m2 <= up_count_running_m1;
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up_count_running_m3 <= up_count_running_m2;
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_d_count <= 'd0;
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up_count_run <= 1'b0;
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end else begin
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if (up_count_running_m3 == 1'b0) begin
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up_count_run <= 1'b1;
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end else if (up_count == 'h00) begin
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up_count_run <= 1'b0;
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end
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if (up_count_capture_s == 1'b1) begin
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up_d_count <= d_count;
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end else if (up_count == 'h00 && up_count_running_m3 == 1'b0) begin
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up_d_count <= 'h00;
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end
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end
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end
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always @(posedge up_clk) begin
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if (up_count_run == 1'b0) begin
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up_count <= 'h01;
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end else begin
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up_count <= up_count + 1'b1;
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end
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end
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// device free running
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// Reset on the rising edge of run
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assign d_count_reset_s = d_count_run_m3 == 1'b0 && d_count_run_m2 == 1'b1;
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always @(posedge d_clk or posedge d_rst) begin
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if (d_rst == 1'b1) begin
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d_count_run_m1 <= 1'b0;
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d_count_run_m2 <= 1'b0;
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d_count_run_m3 <= 1'b0;
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end else begin
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d_count_run_m1 <= up_count_run;
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d_count_run_m2 <= d_count_run_m1;
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d_count_run_m3 <= d_count_run_m2;
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end
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end
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always @(posedge d_clk) begin
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if (d_count_reset_s == 1'b1) begin
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d_count <= 'h00;
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end else if (d_count_run_m3 == 1'b1) begin
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if (d_count[32] == 1'b0) begin
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d_count <= d_count + 1'b1;
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end else begin
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d_count <= {33{1'b1}};
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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