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Lars-Peter Clausen 1ecc5aaffc up_clock_mon: Detect stopped clock 
Currently when the monitored clock stops the clock monitor retains the old
frequency ratio value and there is no way to detect that the clock has
stopped and the reported value is indistinguishable form a clock still
running at the right rate.

If a full iteration as elapsed on the monitoring side and there is no
indication that the counter on the monitored side has started running set
the reported clock ratio value to 0 to indicate that the clock has stopped.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-05-23 11:16:07 +02:00
..
ad_addsub.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_axi_ip_constr.sdc library- altera power up warnings 2016-12-20 16:18:15 -05:00
ad_axis_inf_rx.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_csc_1.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_csc_1_add.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_csc_1_mul.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_csc_CrYCb2RGB.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_csc_RGB2CrYCb.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_datafmt.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_dcfilter.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_dds.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_dds_1.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_dds_sine.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_edge_detect.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_gt_channel.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_gt_channel_1.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_gt_common.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_gt_common_1.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_gt_es.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_gt_es_axi.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_iqcor.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_jesd_align.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_mem.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_mem_asym.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_pnmon.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_rst.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_ss_422to444.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_ss_444to422.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_sysref_gen.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_tdd_control.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
ad_xcvr_rx_if.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ctrlif.vhd Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
axi_streaming_dma_rx_fifo.vhd Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
axi_streaming_dma_tx_fifo.vhd Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
dma_fifo.vhd Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
pl330_dma_fifo.vhd Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
sync_bits.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
sync_gray.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_adc_channel.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_adc_common.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_axi.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_clkgen.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_clock_mon.v up_clock_mon: Detect stopped clock 2017-05-23 11:16:07 +02:00
up_dac_channel.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_dac_common.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_delay_cntrl.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_gt.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_gt_channel.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_hdmi_rx.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_hdmi_tx.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_pmod.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_tdd_cntrl.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_xfer_cntrl.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
up_xfer_status.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_dacfifo_bypass.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_pulse_gen.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00