pluto_hdl_adi/projects/common
Istvan Csomortani 1fce57f6c3 axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
..
a5gt fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers 2017-02-17 15:21:33 -05:00
a5gte a5gte: Fixed timing violations 2016-12-13 10:30:24 +02:00
a5soc common/a5soc- device can not run at 100M cpu clock 2016-11-08 15:19:23 -05:00
a10gx adrv9371x- altera updates 2016-10-27 09:25:00 -04:00
a10soc a10soc - remove default assignments 2016-11-04 15:01:19 -04:00
ac701 common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND 2016-12-09 13:54:39 +02:00
altera projects/altera- qii_auto_pack option 2016-12-22 14:14:21 -05:00
c5soc c5soc- remove unused hps ports 2016-05-09 13:54:08 -04:00
kc705 daq2/all - warnings fix 2016-08-17 10:36:00 -04:00
kcu105 kcu105- added missing ethernet configurations 2017-01-23 10:14:09 -05:00
microzed common: microzed: Add clock, reset and interrupt support 2016-01-13 20:32:26 +01:00
mitx045 version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2 2016-08-29 09:50:46 +03:00
vc707 common/vc707- 2016.2 version 2016-08-17 10:36:19 -04:00
xilinx fifo- as board files 2017-02-22 15:18:50 -05:00
zc702 version_upgrade: Common ZC702 get an upgrade to 2016.2 2016-08-26 10:20:04 +03:00
zc706 axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
zcu102 zcu102/*- actual clock == desired clock 2017-02-06 12:53:47 -05:00
zed version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2 2016-08-29 09:50:46 +03:00
Makefile Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00