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Bogdan Luncan 3f0a487b2e ad9082/vck190: Add initial design 
ADC Mode 27: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS
DAC Mode 35: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 		2023-05-16 12:13:55 +03:00
..
vck190 ad9082/vck190: Add initial design 2023-05-16 12:13:55 +03:00
vcu118 library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
zc706 library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
zcu102 library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
Makefile library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
Readme.md ad9082_fmca_ebz: Readme.md: Remove AD9081 from parts 2021-11-15 13:59:26 +02:00

Readme.md

AD9082-FMCA-EBZ HDL Project

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