Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001		2017-04-13 11:59:55 +03:00
..
Makefile	make updates	2017-03-20 16:05:18 -04:00
system_constr.sdc	daq2/a10gx- xcvr sharing	2016-09-12 14:57:50 -04:00
system_project.tcl	daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V	2017-03-01 11:32:17 +02:00
system_qsys.tcl	projects/altera* - default & common qsys commands	2016-12-20 16:27:44 -05:00
system_top.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00