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laurent-19 553774319a projects/cn0561: Update design: spi trigger, ODR, spi hierch 
* Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 		2023-03-29 15:08:07 +03:00
..
Makefile projects/cn0561: Update design: spi trigger, ODR, spi hierch 2023-03-29 15:08:07 +03:00
system_bd.tcl Updated the makefiles to build the projects in subdirectories based on the build parameters. 2022-11-14 09:38:42 +02:00
system_constr.xdc projects/cn0561: Update design: spi trigger, ODR, spi hierch 2023-03-29 15:08:07 +03:00
system_project.tcl Updated the makefiles to build the projects in subdirectories based on the build parameters. 2022-11-14 09:38:42 +02:00
system_top.v projects: Update .v files according to guideline 2022-06-28 18:06:56 +03:00