Stanca Pop ee30c64923 projects/ad4134_fmc: Initial commit add support ... * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>		2023-03-29 15:08:07 +03:00
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ad4134_bd.tcl	projects/ad4134_fmc: Initial commit add support	2023-03-29 15:08:07 +03:00