282 lines
12 KiB
Tcl
282 lines
12 KiB
Tcl
# a10soc carrier qsys
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set system_type a10soc
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# clock-&-reset
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add_instance sys_clk clock_source
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add_interface sys_clk clock sink
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set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
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add_interface sys_rstn reset sink
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set_interface_property sys_rstn EXPORT_OF sys_clk.clk_in_reset
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set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
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set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
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set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
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# hps
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# round-about way - qsys-script doesn't support {*}?
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variable hps_io_list
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proc set_hps_io {io_index io_type} {
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global hps_io_list
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lappend hps_io_list $io_type
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}
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set_hps_io IO_DEDICATED_04 SDMMC:D0
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set_hps_io IO_DEDICATED_05 SDMMC:CMD
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set_hps_io IO_DEDICATED_06 SDMMC:CCLK
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set_hps_io IO_DEDICATED_07 SDMMC:D1
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set_hps_io IO_DEDICATED_08 SDMMC:D2
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set_hps_io IO_DEDICATED_09 SDMMC:D3
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set_hps_io IO_DEDICATED_10 NONE
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set_hps_io IO_DEDICATED_11 NONE
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set_hps_io IO_DEDICATED_12 SDMMC:D4
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set_hps_io IO_DEDICATED_13 SDMMC:D5
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set_hps_io IO_DEDICATED_14 SDMMC:D6
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set_hps_io IO_DEDICATED_15 SDMMC:D7
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set_hps_io IO_DEDICATED_16 UART1:TX
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set_hps_io IO_DEDICATED_17 UART1:RX
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set_hps_io IO_SHARED_Q1_01 USB0:CLK
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set_hps_io IO_SHARED_Q1_02 USB0:STP
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set_hps_io IO_SHARED_Q1_03 USB0:DIR
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set_hps_io IO_SHARED_Q1_04 USB0:DATA0
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set_hps_io IO_SHARED_Q1_05 USB0:DATA1
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set_hps_io IO_SHARED_Q1_06 USB0:NXT
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set_hps_io IO_SHARED_Q1_07 USB0:DATA2
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set_hps_io IO_SHARED_Q1_08 USB0:DATA3
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set_hps_io IO_SHARED_Q1_09 USB0:DATA4
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set_hps_io IO_SHARED_Q1_10 USB0:DATA5
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set_hps_io IO_SHARED_Q1_11 USB0:DATA6
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set_hps_io IO_SHARED_Q1_12 USB0:DATA7
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set_hps_io IO_SHARED_Q2_01 EMAC0:TX_CLK
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set_hps_io IO_SHARED_Q2_02 EMAC0:TX_CTL
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set_hps_io IO_SHARED_Q2_03 EMAC0:RX_CLK
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set_hps_io IO_SHARED_Q2_04 EMAC0:RX_CTL
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set_hps_io IO_SHARED_Q2_05 EMAC0:TXD0
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set_hps_io IO_SHARED_Q2_06 EMAC0:TXD1
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set_hps_io IO_SHARED_Q2_07 EMAC0:RXD0
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set_hps_io IO_SHARED_Q2_08 EMAC0:RXD1
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set_hps_io IO_SHARED_Q2_09 EMAC0:TXD2
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set_hps_io IO_SHARED_Q2_10 EMAC0:TXD3
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set_hps_io IO_SHARED_Q2_11 EMAC0:RXD2
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set_hps_io IO_SHARED_Q2_12 EMAC0:RXD3
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set_hps_io IO_SHARED_Q3_01 NONE
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set_hps_io IO_SHARED_Q3_02 NONE
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set_hps_io IO_SHARED_Q3_03 NONE
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set_hps_io IO_SHARED_Q3_04 NONE
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set_hps_io IO_SHARED_Q3_05 NONE
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set_hps_io IO_SHARED_Q3_06 GPIO
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set_hps_io IO_SHARED_Q3_07 NONE
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set_hps_io IO_SHARED_Q3_08 NONE
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set_hps_io IO_SHARED_Q3_09 NONE
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set_hps_io IO_SHARED_Q3_10 NONE
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set_hps_io IO_SHARED_Q3_11 MDIO0:MDIO
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set_hps_io IO_SHARED_Q3_12 MDIO0:MDC
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set_hps_io IO_SHARED_Q4_01 I2C1:SDA
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set_hps_io IO_SHARED_Q4_02 I2C1:SCL
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set_hps_io IO_SHARED_Q4_03 GPIO
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set_hps_io IO_SHARED_Q4_04 NONE
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set_hps_io IO_SHARED_Q4_05 GPIO
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set_hps_io IO_SHARED_Q4_06 GPIO
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set_hps_io IO_SHARED_Q4_07 NONE
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set_hps_io IO_SHARED_Q4_08 NONE
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set_hps_io IO_SHARED_Q4_09 NONE
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set_hps_io IO_SHARED_Q4_10 NONE
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set_hps_io IO_SHARED_Q4_11 NONE
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set_hps_io IO_SHARED_Q4_12 NONE
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add_instance sys_hps altera_arria10_hps
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set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
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set_instance_parameter_value sys_hps {F2S_Width} {0}
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set_instance_parameter_value sys_hps {S2F_Width} {0}
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set_instance_parameter_value sys_hps {LWH2F_Enable} {1}
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set_instance_parameter_value sys_hps {F2SDRAM_PORT_CONFIG} {6}
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set_instance_parameter_value sys_hps {F2SDRAM0_ENABLED} {1}
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set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
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set_instance_parameter_value sys_hps {HPS_IO_Enable} $hps_io_list
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set_instance_parameter_value sys_hps {SDMMC_PinMuxing} {IO}
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set_instance_parameter_value sys_hps {SDMMC_Mode} {8-bit}
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set_instance_parameter_value sys_hps {USB0_PinMuxing} {IO}
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set_instance_parameter_value sys_hps {USB0_Mode} {default}
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set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {IO}
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set_instance_parameter_value sys_hps {EMAC0_Mode} {RGMII_with_MDIO}
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set_instance_parameter_value sys_hps {UART1_PinMuxing} {IO}
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set_instance_parameter_value sys_hps {UART1_Mode} {No_flow_control}
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set_instance_parameter_value sys_hps {I2C1_PinMuxing} {IO}
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set_instance_parameter_value sys_hps {I2C1_Mode} {default}
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set_instance_parameter_value sys_hps {F2H_COLD_RST_Enable} {1}
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set_instance_parameter_value sys_hps {H2F_USER0_CLK_Enable} {1}
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set_instance_parameter_value sys_hps {H2F_USER0_CLK_FREQ} {175}
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set_instance_parameter_value sys_hps {CLK_SDMMC_SOURCE} {1}
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add_interface sys_hps_rstn reset sink
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set_interface_property sys_hps_rstn EXPORT_OF sys_hps.f2h_cold_reset_req
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add_interface sys_hps_out_rstn reset source
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set_interface_property sys_hps_out_rstn EXPORT_OF sys_hps.h2f_reset
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add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
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add_connection sys_clk.clk_reset sys_hps.h2f_lw_axi_reset
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add_interface sys_hps_io conduit end
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set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io
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# common dma interfaces
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add_instance sys_dma_clk clock_source
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set_instance_parameter_value sys_dma_clk {resetSynchronousEdges} {DEASSERT}
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set_instance_parameter_value sys_dma_clk {clockFrequencyKnown} {false}
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add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
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add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
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add_connection sys_dma_clk.clk sys_hps.f2sdram0_clock
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add_connection sys_dma_clk.clk_reset sys_hps.f2sdram0_reset
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# ddr4 interface
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add_instance sys_hps_ddr4_cntrl altera_emif_a10_hps
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set_instance_parameter_value sys_hps_ddr4_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR4}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_BANK_GROUP_WIDTH} {1}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_DATA_LANES}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_DQS_GROUP} {3}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_READ_DBI} {1}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TCL} {20}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_WTCL} {18}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_6}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_IO} {0}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_LVDS_NO_OCT}
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set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRCD_NS} {14.25}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRP_NS} {14.25}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_S_CYC} {7}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_L_CYC} {8}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TFAW_NS} {30.0}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_S_CYC} {4}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_L_CYC} {10}
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set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {1D}
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set_instance_parameter_value sys_hps_ddr4_cntrl {DIAG_DDR4_SKIP_CA_LEVEL} {1}
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set_instance_parameter_value sys_hps_ddr4_cntrl {SHORT_QSYS_INTERFACE_NAMES} {0}
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add_interface sys_hps_ddr_rstn reset sink
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set_interface_property sys_hps_ddr_rstn EXPORT_OF sys_hps_ddr4_cntrl.global_reset_reset_sink
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add_connection sys_hps_ddr4_cntrl.hps_emif_conduit_end sys_hps.emif
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add_interface sys_hps_ddr conduit end
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set_interface_property sys_hps_ddr EXPORT_OF sys_hps_ddr4_cntrl.mem_conduit_end
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add_interface sys_hps_ddr_oct conduit end
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set_interface_property sys_hps_ddr_oct EXPORT_OF sys_hps_ddr4_cntrl.oct_conduit_end
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add_interface sys_hps_ddr_ref_clk clock sink
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set_interface_property sys_hps_ddr_ref_clk EXPORT_OF sys_hps_ddr4_cntrl.pll_ref_clk_clock_sink
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# cpu/hps handling
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proc ad_cpu_interrupt {m_irq m_port} {
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add_connection sys_hps.f2h_irq0 ${m_port}
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set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
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}
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proc ad_cpu_interconnect {m_base m_port} {
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add_connection sys_hps.h2f_lw_axi_master ${m_port}
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set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
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}
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proc ad_dma_interconnect {m_port} {
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add_connection ${m_port} sys_hps.f2sdram0_data
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set_connection_parameter_value ${m_port}/sys_hps.f2sdram0_data baseAddress {0x0}
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}
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# gpio-bd
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add_instance sys_gpio_bd altera_avalon_pio
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set_instance_parameter_value sys_gpio_bd {direction} {InOut}
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set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
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set_instance_parameter_value sys_gpio_bd {width} {32}
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add_connection sys_clk.clk_reset sys_gpio_bd.reset
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add_connection sys_clk.clk sys_gpio_bd.clk
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add_interface sys_gpio_bd conduit end
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set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
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# gpio-in
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add_instance sys_gpio_in altera_avalon_pio
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set_instance_parameter_value sys_gpio_in {direction} {Input}
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set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
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set_instance_parameter_value sys_gpio_in {width} {32}
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add_connection sys_clk.clk_reset sys_gpio_in.reset
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add_connection sys_clk.clk sys_gpio_in.clk
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add_interface sys_gpio_in conduit end
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set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
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# gpio-out
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add_instance sys_gpio_out altera_avalon_pio
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set_instance_parameter_value sys_gpio_out {direction} {Output}
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set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
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set_instance_parameter_value sys_gpio_out {width} {32}
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add_connection sys_clk.clk_reset sys_gpio_out.reset
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add_connection sys_clk.clk sys_gpio_out.clk
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add_interface sys_gpio_out conduit end
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set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
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# spi
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add_instance sys_spi altera_avalon_spi
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set_instance_parameter_value sys_spi {clockPhase} {0}
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set_instance_parameter_value sys_spi {clockPolarity} {0}
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set_instance_parameter_value sys_spi {dataWidth} {8}
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set_instance_parameter_value sys_spi {masterSPI} {1}
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set_instance_parameter_value sys_spi {numberOfSlaves} {8}
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set_instance_parameter_value sys_spi {targetClockRate} {10000000.0}
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add_connection sys_clk.clk_reset sys_spi.reset
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add_connection sys_clk.clk sys_spi.clk
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add_interface sys_spi conduit end
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set_interface_property sys_spi EXPORT_OF sys_spi.external
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# system id
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add_instance axi_sysid_0 axi_sysid
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add_instance rom_sys_0 sysid_rom
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add_connection axi_sysid_0.if_rom_addr rom_sys_0.if_rom_addr
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add_connection rom_sys_0.if_rom_data axi_sysid_0.if_sys_rom_data
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add_connection sys_clk.clk rom_sys_0.if_clk
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add_connection sys_clk.clk axi_sysid_0.s_axi_clock
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add_connection sys_clk.clk_reset axi_sysid_0.s_axi_reset
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add_interface pr_rom_data_nc conduit end
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set_interface_property pr_rom_data_nc EXPORT_OF axi_sysid_0.if_pr_rom_data
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# base-addresses
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ad_cpu_interconnect 0x000000d0 sys_gpio_bd.s1
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ad_cpu_interconnect 0x00000000 sys_gpio_in.s1
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ad_cpu_interconnect 0x00000020 sys_gpio_out.s1
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ad_cpu_interconnect 0x00000040 sys_spi.spi_control_port
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ad_cpu_interconnect 0x00018000 axi_sysid_0.s_axi
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# interrupts
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ad_cpu_interrupt 5 sys_gpio_in.irq
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ad_cpu_interrupt 6 sys_gpio_bd.irq
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ad_cpu_interrupt 7 sys_spi.irq
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# architecture specific global variables
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set xcvr_reconfig_addr_width 10
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