41 lines
2.0 KiB
Tcl
41 lines
2.0 KiB
Tcl
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# pl ddr3 (use only when dma is not capable of keeping up).
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# generic fifo interface - existence is oblivious to software.
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create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen
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create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl
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file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \
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[get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]]
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set_property CONFIG.XML_INPUT_FILE {zc706_plddr3_mig.prj} [get_bd_cells axi_ddr_cntrl]
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create_bd_port -dir I -type rst sys_rst
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set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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ad_connect sys_rst axi_ddr_cntrl/sys_rst
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ad_connect sys_clk axi_ddr_cntrl/SYS_CLK
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ad_connect ddr3 axi_ddr_cntrl/DDR3
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create_bd_cell -type ip -vlnv analog.com:user:axi_dacfifo:1.0 $dac_fifo_name
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set_property CONFIG.DAC_DATA_WIDTH $dac_data_width [get_bd_cells $dac_fifo_name]
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set_property CONFIG.DMA_DATA_WIDTH $dac_dma_data_width [get_bd_cells $dac_fifo_name]
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set_property CONFIG.AXI_DATA_WIDTH {512} [get_bd_cells $dac_fifo_name]
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set_property CONFIG.AXI_SIZE {6} [get_bd_cells $dac_fifo_name]
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set_property CONFIG.AXI_LENGTH {15} [get_bd_cells $dac_fifo_name]
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set_property CONFIG.AXI_ADDRESS {0x80000000} [get_bd_cells $dac_fifo_name]
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set_property CONFIG.AXI_ADDRESS_LIMIT {0xa0000000} [get_bd_cells $dac_fifo_name]
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ad_connect axi_ddr_cntrl/S_AXI $dac_fifo_name/axi
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ad_connect axi_ddr_cntrl/ui_clk $dac_fifo_name/axi_clk
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ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk
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ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in
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ad_connect axi_rstgen/peripheral_aresetn $dac_fifo_name/axi_resetn
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ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn
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ad_connect axi_ddr_cntrl/device_temp_i GND
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assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
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