347 lines
12 KiB
VHDL
347 lines
12 KiB
VHDL
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Copyright 2011-2013(c) Analog Devices, Inc.
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--
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- - Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- - Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in
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-- the documentation and/or other materials provided with the
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-- distribution.
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-- - Neither the name of Analog Devices, Inc. nor the names of its
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-- contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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-- - The use of this software may or may not infringe the patent rights
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-- of one or more patent holders. This license does not release you
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-- from the requirement that you obtain separate licenses from these
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-- patent holders to use this software.
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-- - Use of the software either in source or binary form, must be run
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-- on or directly connected to an Analog Devices Inc. component.
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--
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-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED.
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--
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-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- andrei.cozma@analog.com (c) Analog Devices Inc.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.tx_package.all;
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use work.axi_ctrlif;
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use work.axi_streaming_dma_tx_fifo;
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use work.pl330_dma_fifo;
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entity axi_spdif_tx is
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generic (
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S_AXI_DATA_WIDTH : integer := 32;
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S_AXI_ADDRESS_WIDTH : integer := 32;
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DEVICE_FAMILY : string := "virtex6";
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DMA_TYPE : integer := 0
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);
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port (
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--SPDIF ports
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spdif_data_clk : in std_logic;
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spdif_tx_o : out std_logic;
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--AXI Lite interface
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s_axi_aclk : in std_logic;
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s_axi_aresetn : in std_logic;
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s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_awprot : in std_logic_vector(2 downto 0);
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s_axi_awvalid : in std_logic;
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s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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s_axi_wvalid : in std_logic;
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s_axi_bready : in std_logic;
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s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_arprot : in std_logic_vector(2 downto 0);
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s_axi_arvalid : in std_logic;
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s_axi_rready : in std_logic;
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s_axi_arready : out std_logic;
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s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_rresp : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic;
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s_axi_wready : out std_logic;
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s_axi_bresp : out std_logic_vector(1 downto 0);
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s_axi_bvalid : out std_logic;
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s_axi_awready : out std_logic;
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--axi streaming interface
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s_axis_aclk : in std_logic;
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s_axis_aresetn : in std_logic;
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s_axis_tready : out std_logic;
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s_axis_tdata : in std_logic_vector(31 downto 0);
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s_axis_tlast : in std_logic;
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s_axis_tvalid : in std_logic;
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--PL330 DMA interface
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dma_req_aclk : in std_logic;
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dma_req_rstn : in std_logic;
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dma_req_davalid : in std_logic;
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dma_req_datype : in std_logic_vector(1 downto 0);
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dma_req_daready : out std_logic;
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dma_req_drvalid : out std_logic;
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dma_req_drtype : out std_logic_vector(1 downto 0);
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dma_req_drlast : out std_logic;
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dma_req_drready : in std_logic
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);
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end entity axi_spdif_tx;
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------------------------------------------------------------------------------
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-- Architecture section
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------------------------------------------------------------------------------
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architecture IMP of axi_spdif_tx is
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------------------------------------------
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-- SPDIF signals
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------------------------------------------
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signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstat_freq : std_logic_vector(1 downto 0);
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signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
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signal sample_data_ack : std_logic;
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signal sample_data: std_logic_vector(15 downto 0);
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signal conf_mode : std_logic_vector(3 downto 0);
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signal conf_ratio : std_logic_vector(7 downto 0);
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signal conf_tinten, conf_txdata, conf_txen : std_logic;
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signal channel : std_logic;
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signal enable : boolean;
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signal fifo_data_out : std_logic_vector(31 downto 0);
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signal fifo_data_ack : std_logic;
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signal fifo_reset : std_logic;
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signal tx_fifo_stb : std_logic;
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-- Register access
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signal wr_data : std_logic_vector(31 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : integer range 0 to 3;
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signal rd_addr : integer range 0 to 3;
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signal wr_stb : std_logic;
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signal rd_ack : std_logic;
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begin
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fifo_reset <= not conf_txdata;
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enable <= conf_txdata = '1';
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fifo_data_ack <= channel and sample_data_ack;
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streaming_dma_gen: if DMA_TYPE = 0 generate
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fifo: entity axi_streaming_dma_tx_fifo
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generic map (
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => fifo_reset,
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enable => enable,
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s_axis_aclk => s_axis_aclk,
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s_axis_tready => s_axis_tready,
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s_axis_tdata => s_axis_tdata,
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s_axis_tvalid => s_axis_tlast,
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s_axis_tlast => s_axis_tvalid,
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out_ack => fifo_data_ack,
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out_data => fifo_data_out
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);
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end generate;
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no_streaming_dma_gen: if DMA_TYPE /= 0 generate
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s_axis_tready <= '0';
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end generate;
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pl330_dma_gen: if DMA_TYPE = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
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fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32,
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FIFO_DIRECTION => 0
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => fifo_reset,
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enable => enable,
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in_data => wr_data,
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in_stb => tx_fifo_stb,
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out_ack => fifo_data_ack,
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out_data => fifo_data_out,
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dclk => dma_req_aclk,
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dresetn => dma_req_rstn,
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davalid => dma_req_davalid,
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daready => dma_req_daready,
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datype => dma_req_datype,
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drvalid => dma_req_drvalid,
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drready => dma_req_drreadY,
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drtype => dma_req_drtype,
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drlast => dma_req_drlast
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);
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end generate;
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no_pl330_dma_gen: if DMA_TYPE /= 1 generate
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dma_req_daready <= '0';
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dma_req_drvalid <= '0';
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dma_req_drtype <= (others => '0');
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dma_req_drlast <= '0';
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end generate;
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sample_data_mux: process (fifo_data_out, channel) is
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begin
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if channel = '0' then
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sample_data <= fifo_data_out(15 downto 0);
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else
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sample_data <= fifo_data_out(31 downto 16);
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end if;
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end process;
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-- Configuration signals update
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conf_mode(3 downto 0) <= config_reg(23 downto 20);
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conf_ratio(7 downto 0) <= config_reg(15 downto 8);
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conf_tinten <= config_reg(2);
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conf_txdata <= config_reg(1);
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conf_txen <= config_reg(0);
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-- Channel status signals update
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chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
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chstat_gstat <= chstatus_reg(3);
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chstat_preem <= chstatus_reg(2);
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chstat_copy <= chstatus_reg(1);
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chstat_audio <= chstatus_reg(0);
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-- Transmit encoder
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TENC: tx_encoder
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generic map (
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DATA_WIDTH => 16
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)
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port map (
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up_clk => s_axi_aclk,
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data_clk => spdif_data_clk, -- data clock
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resetn => s_axi_aresetn, -- resetn
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conf_mode => conf_mode, -- sample format
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conf_ratio => conf_ratio, -- clock divider
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conf_txdata => conf_txdata, -- sample data enable
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conf_txen => conf_txen, -- spdif signal enable
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chstat_freq => chstat_freq, -- sample freq.
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chstat_gstat => chstat_gstat, -- generation status
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chstat_preem => chstat_preem, -- preemphasis status
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chstat_copy => chstat_copy, -- copyright bit
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chstat_audio => chstat_audio, -- data format
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sample_data => sample_data, -- audio data
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sample_data_ack => sample_data_ack, -- sample buffer read
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channel => channel, -- which channel should be read
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spdif_tx_o => spdif_tx_o -- SPDIF output signal
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);
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ctrlif: entity axi_ctrlif
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generic map (
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C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
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C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
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C_NUM_REG => 4
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)
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port map(
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s_axi_aclk => s_axi_aclk,
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s_axi_aresetn => s_axi_aresetn,
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s_axi_awaddr => s_axi_awaddr,
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s_axi_awvalid => s_axi_awvalid,
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s_axi_wdata => s_axi_wdata,
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s_axi_wstrb => s_axi_wstrb,
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s_axi_wvalid => s_axi_wvalid,
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s_axi_bready => s_axi_bready,
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s_axi_araddr => s_axi_araddr,
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s_axi_arvalid => s_axi_arvalid,
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s_axi_rready => s_axi_rready,
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s_axi_arready => s_axi_arready,
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s_axi_rdata => s_axi_rdata,
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s_axi_rresp => s_axi_rresp,
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s_axi_rvalid => s_axi_rvalid,
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s_axi_wready => s_axi_wready,
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s_axi_bresp => s_axi_bresp,
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s_axi_bvalid => s_axi_bvalid,
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s_axi_awready => s_axi_awready,
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rd_addr => rd_addr,
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rd_data => rd_data,
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rd_ack => rd_ack,
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rd_stb => '1',
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wr_addr => wr_addr,
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wr_data => wr_data,
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wr_ack => '1',
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wr_stb => wr_stb
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);
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process (s_axi_aclk)
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begin
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if rising_edge(s_axi_aclk) then
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if s_axi_aresetn = '0' then
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config_reg <= (others => '0');
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chstatus_reg <= (others => '0');
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else
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if wr_stb = '1' then
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case wr_addr is
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when 0 => config_reg <= wr_data;
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when 1 => chstatus_reg <= wr_data;
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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process (rd_addr, config_reg, chstatus_reg)
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begin
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case rd_addr is
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when 0 => rd_data <= config_reg;
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when 1 => rd_data <= chstatus_reg;
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when others => rd_data <= (others => '0');
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end case;
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end process;
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end IMP;
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