120 lines
4.0 KiB
Tcl
120 lines
4.0 KiB
Tcl
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# RX parameters
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 4 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_ad9656_rx_xcvr [list \
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NUM_OF_LANES $RX_NUM_OF_LANES \
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QPLL_ENABLE 1 \
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TX_OR_RX_N 0 \
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SYS_CLK_SEL 0 \
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OUT_CLK_SEL 4 \
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]
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adi_axi_jesd204_rx_create axi_ad9656_rx_jesd $RX_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_ad9656_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create rx_ad9656_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_ad9656_rx_dma [list \
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DMA_TYPE_SRC 2 \
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DMA_TYPE_DEST 0 \
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CYCLIC 0 \
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SYNC_TRANSFER_START 1 \
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DMA_2D_TRANSFER 0 \
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DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES] \
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MAX_BYTES_PER_BURST 256 \
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AXI_SLICE_DEST false \
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AXI_SLICE_SRC false \
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DMA_DATA_WIDTH_DEST 128 \
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FIFO_SIZE 32 \
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]
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# common cores
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ad_ip_instance util_adxcvr util_ad9656_xcvr [list \
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RX_NUM_OF_LANES $RX_NUM_OF_LANES \
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TX_NUM_OF_LANES 0 \
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CPLL_FBDIV 4 \
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CPLL_FBDIV_4_5 5 \
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RX_OUT_DIV 2 \
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RX_CLK25_DIV 5 \
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]
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# xcvr interfaces
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set rx_ref_clk rx_ref_clk_0
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create_bd_port -dir I $rx_ref_clk
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ad_connect $sys_cpu_resetn util_ad9656_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_ad9656_xcvr/up_clk
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# Rx
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ad_connect ad9656_rx_device_clk util_ad9656_xcvr/rx_out_clk_0
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ad_xcvrcon util_ad9656_xcvr axi_ad9656_rx_xcvr axi_ad9656_rx_jesd {} ad9656_rx_device_clk
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ad_xcvrpll $rx_ref_clk util_ad9656_xcvr/qpll_ref_clk_0
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for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
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set ch [expr $i]
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ad_xcvrpll $rx_ref_clk util_ad9656_xcvr/cpll_ref_clk_$ch
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ad_xcvrpll axi_ad9656_rx_xcvr/up_pll_rst util_ad9656_xcvr/up_cpll_rst_$ch
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}
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# connections (adc)
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ad_connect util_ad9656_xcvr/rx_out_clk_0 rx_ad9656_tpl_core/link_clk
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ad_connect axi_ad9656_rx_jesd/rx_sof rx_ad9656_tpl_core/link_sof
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ad_connect axi_ad9656_rx_jesd/rx_data_tdata rx_ad9656_tpl_core/link_data
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ad_connect axi_ad9656_rx_jesd/rx_data_tvalid rx_ad9656_tpl_core/link_valid
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ad_connect util_ad9656_xcvr/rx_out_clk_0 util_ad9656_rx_cpack/clk
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ad_connect ad9656_rx_device_clk_rstgen/peripheral_reset util_ad9656_rx_cpack/reset
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ad_connect rx_ad9656_tpl_core/adc_valid_0 util_ad9656_rx_cpack/fifo_wr_en
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ad_connect rx_ad9656_tpl_core/adc_enable_0 util_ad9656_rx_cpack/enable_0
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ad_connect rx_ad9656_tpl_core/adc_enable_1 util_ad9656_rx_cpack/enable_1
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ad_connect rx_ad9656_tpl_core/adc_enable_2 util_ad9656_rx_cpack/enable_2
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ad_connect rx_ad9656_tpl_core/adc_enable_3 util_ad9656_rx_cpack/enable_3
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ad_connect rx_ad9656_tpl_core/adc_data_0 util_ad9656_rx_cpack/fifo_wr_data_0
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ad_connect rx_ad9656_tpl_core/adc_data_1 util_ad9656_rx_cpack/fifo_wr_data_1
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ad_connect rx_ad9656_tpl_core/adc_data_2 util_ad9656_rx_cpack/fifo_wr_data_2
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ad_connect rx_ad9656_tpl_core/adc_data_3 util_ad9656_rx_cpack/fifo_wr_data_3
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ad_connect rx_ad9656_tpl_core/adc_dovf util_ad9656_rx_cpack/fifo_wr_overflow
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ad_connect util_ad9656_xcvr/rx_out_clk_0 axi_ad9656_rx_dma/fifo_wr_clk
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ad_connect util_ad9656_rx_cpack/packed_fifo_wr axi_ad9656_rx_dma/fifo_wr
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ad_connect $sys_dma_resetn axi_ad9656_rx_dma/m_dest_axi_aresetn
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A00000 rx_ad9656_tpl_core
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ad_cpu_interconnect 0x44A60000 axi_ad9656_rx_xcvr
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ad_cpu_interconnect 0x44AA0000 axi_ad9656_rx_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9656_rx_dma
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ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9656_rx_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
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ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-12 mb-13 axi_ad9656_rx_jesd/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9656_rx_dma/irq
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