173f4a83d4
- ad_serdes_in:
* Removed unused ports: loaden, phase, locked
* Added IODELAY_ENABLE is set to be by default 1
* Added conditional instantiation (using IODELAY_ENABLE) to IDELAY modules
* Added conditional instantiation (using IODELAY_CTRL_ENABLED) to IDELAYCTRL module, based on IODELAY_ENABLE
- library: Update ad_serdes_in instances: add IODELAY_ENABLE
* Edited in:
* axi_ad9434
* axi_ad9684
* axi_adrv9001
- ad_serdes_out:
* Removed unused port: loaden
- library: Update ad_serdes_out instances
* Edited in:
* axi_ad9122
* axi_ad9739a
* axi_ad9783
* axi_adrv9001
- ad_serdes_clk:
* Remove unused ports: loaden, phase
- library: Update ad_serdes_clk instances
* Edited in:
* axi_ad9122
* axi_ad9434
* axi_ad9684
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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|---|---|---|
| .github | ||
| docs | ||
| library | ||
| projects | ||
| scripts | ||
| .gitattributes | ||
| .gitignore | ||
| LICENSE | ||
| LICENSE_ADIBSD | ||
| LICENSE_BSD-1-Clause | ||
| LICENSE_GPL2 | ||
| LICENSE_LGPL | ||
| Makefile | ||
| README.md | ||
| quiet.mk | ||
README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects for various reference design and prototyping systems. This repository contains HDL code (Verilog or VHDL) and the required Tcl scripts to create and build a specific FPGA example design using Xilinx and/or Intel tool chain.
Support
The HDL is provided "AS IS", support is only provided on EngineerZone.
If you feel you can not, or do not want to ask questions on EngineerZone, you should not use or look at the HDL found in this repository. Just like you have the freedom and rights to use this software in your products (with the obligations found in individual licenses) and get support on EngineerZone, you have the freedom and rights not to use this software and get datasheet level support from traditional ADI contacts that you may have.
There is no free replacement for consulting services. If you have questions that are best handed one-on-one engagement, and are time sensitive, consider hiring a consultant. If you want to find a consultant who is familar with the HDL found in this repository - ask on EngineerZone.
Getting started
This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.
Prerequisites
or
Please make sure that you have the required tool version.
How to build a project
For building a project (generate a bitstream), you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.
To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:
[~]cd projects/fmcomms2/zc706
[~]make
A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build
Software
In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.
Which branch should I use?
-
If you want to use the most stable code base, always use the latest release branch.
-
If you want to use the greatest and latest, check out the master branch.
Use already built files
You can download already built files and use them as they are. They are available on this link.
The files are built from master branch whenever there are new commits in HDL or Linux repositories.
⚠️ Pay attention when using already built files, since they are not tested in HW!
License
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
See LICENSE for more details. The separate license files cab be found here:
Comprehensive user guide
See HDL User Guide for a more detailed guide.