Istvan Csomortani 9afc871b70 a10gx: Optimise the base design ... Add a clock crossing bridge for the interfaces that runs on a different clock than the emif_user_clk. This way we can simplify the main interconnect, and prevent occasional timing violations.		2019-06-04 11:28:37 +03:00
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a10gx	a10gx: Optimise the base design	2019-06-04 11:28:37 +03:00
a10soc	adcfifo/dacfifo: fix alignments	2019-01-23 14:45:45 +02:00
ac701	microblaze: add SPI clock constraint	2019-05-30 14:55:11 +03:00
altera	adcfifo/dacfifo: fix alignments	2019-01-23 14:45:45 +02:00
c5soc	Remove executable flag from non-executable files	2017-07-28 17:56:07 +02:00
de10	DE10: Initial commit	2018-04-11 15:09:54 +03:00
kc705	microblaze: add SPI clock constraint	2019-05-30 14:55:11 +03:00
kcu105	microblaze: add SPI clock constraint	2019-05-30 14:55:11 +03:00
microzed	Remove interrupts from system_top for all xilinx projects	2018-08-10 10:10:58 +03:00
vc707	microblaze: add SPI clock constraint	2019-05-30 14:55:11 +03:00
vcu118	microblaze: add SPI clock constraint	2019-05-30 14:55:11 +03:00
xilinx	adcfifo/dacfifo: fix alignments	2019-01-23 14:45:45 +02:00
zc702	zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS	2019-05-30 14:55:11 +03:00
zc706	zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS	2019-05-30 14:55:11 +03:00
zcu102	zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS	2019-05-30 14:55:11 +03:00
zed	zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS	2019-05-30 14:55:11 +03:00