Istvan Csomortani 11822e2824 cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line ... Note, the current SCLK to spi_clk ratio is four. That means, the input delay in the MISO line is 25% of the SCLK period. If the SCLK to spi_clk ratio is changing, this constraint must be updated.		2020-10-02 10:50:06 +03:00
..
Makefile	cn0540: Initial commit	2020-05-28 18:49:35 +03:00
system_bd.tcl	sysid: Remove cstring init string	2020-09-30 19:12:24 +03:00
system_constr.xdc	cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line	2020-10-02 10:50:06 +03:00
system_project.tcl	cn0540: Fix typo	2020-06-04 18:38:14 +03:00
system_top.v	cn0540: Initial commit	2020-05-28 18:49:35 +03:00