Istvan Csomortani 11822e2824 cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line ... Note, the current SCLK to spi_clk ratio is four. That means, the input delay in the MISO line is 25% of the SCLK period. If the SCLK to spi_clk ratio is changing, this constraint must be updated.		2020-10-02 10:50:06 +03:00
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common	cn0540/bd: Generate a 80MHz spi_clk	2020-10-02 10:50:06 +03:00
coraz7s	cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line	2020-10-02 10:50:06 +03:00
de10nano	cn0540/de10nano: Ignore 15003 critical warning	2020-09-25 12:56:53 +03:00
Makefile	cn0540: Initial commit	2020-05-28 18:49:35 +03:00