pluto_hdl_adi/library/altera/common/ad_lvds_clk.v

90 lines
3.2 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk (
rst,
locked,
clk_in_p,
clk_in_n,
clk);
parameter DEVICE_TYPE = 0;
input rst;
output locked;
input clk_in_p;
input clk_in_n;
output clk;
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_clk i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk_0 (clk),
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("lvds"),
.number_of_clocks(1),
.output_clock_frequency0("250.0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk (clk),
.locked (locked));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************