pluto_hdl_adi/projects/ad6676evb
Istvan Csomortani ac2e5a9dac constraints: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
..
common
vc707 constraints: Update constraints 2017-02-24 13:43:32 +02:00
zc706 constraints: Update constraints 2017-02-24 13:43:32 +02:00
Makefile