104e49d515
The address width for the AXI-Lite configuration bus for the core is only 14 bit. Remove the upper unused bits from the public interface. This allows infrastructure code to know about this and it might be able to perform optimizations of the interconnect based on this. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- Xilinx : Vivado 2014.4.1
- Altera : Quartus 15.0
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.