bfc8ec28c3
In cases when a shallow FIFO is requested the synthesizer infers distributed RAM instead of block RAMs. This can be an issue when the clocks of the FIFO are asynchronous since a timing path is created though the LUTs which implement the memory, resulting in timing failures. Ignoring timing through the path is not a solution since would lead to metastability. This does not happens with block RAMs. The solution is to use the ad_mem (block RAM) in case of async clocks and letting the synthesizer do it's job in case of sync clocks for optimal resource utilization. |
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| .. | ||
| avl_dacfifo.v | ||
| avl_dacfifo_byteenable_coder.v | ||
| avl_dacfifo_byteenable_decoder.v | ||
| avl_dacfifo_constr.sdc | ||
| avl_dacfifo_hw.tcl | ||
| avl_dacfifo_rd.v | ||
| avl_dacfifo_wr.v | ||
| util_dacfifo_bypass.v | ||