73 lines
2.0 KiB
Verilog
73 lines
2.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_lvds_clk #(
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parameter DEVICE_TYPE = 0) (
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input rst,
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output locked,
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input clk_in_p,
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input clk_in_n,
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output clk);
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localparam SERIES7 = 0;
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localparam VIRTEX6 = 1;
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// wires
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wire clk_ibuf_s;
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// defaults
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assign locked = 1'b1;
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// instantiations
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IBUFGDS i_rx_clk_ibuf (
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.I (clk_in_p),
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.IB (clk_in_n),
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.O (clk_ibuf_s));
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generate
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if (DEVICE_TYPE == VIRTEX6) begin
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BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (clk_ibuf_s),
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.O (clk));
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end else begin
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BUFG i_clk_gbuf (
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.I (clk_ibuf_s),
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.O (clk));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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