300 lines
9.4 KiB
Verilog
300 lines
9.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dacfifo #(
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parameter DAC_DATA_WIDTH = 64,
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parameter DMA_DATA_WIDTH = 64,
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parameter AXI_DATA_WIDTH = 512,
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parameter AXI_SIZE = 2,
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parameter AXI_LENGTH = 15,
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parameter AXI_ADDRESS = 32'h00000000,
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parameter AXI_ADDRESS_LIMIT = 32'hffffffff) (
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// dma interface (AXI Stream)
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input dma_clk,
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input dma_rst,
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input dma_valid,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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output reg dma_ready,
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input dma_xfer_req,
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input dma_xfer_last,
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// dac interface
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input dac_clk,
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input dac_rst,
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input dac_valid,
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output reg [(DAC_DATA_WIDTH-1):0] dac_data,
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output reg dac_dunf,
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output reg dac_xfer_out,
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input bypass,
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// axi interface
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input axi_clk,
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input axi_resetn,
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output axi_awvalid,
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output [ 3:0] axi_awid,
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output [ 1:0] axi_awburst,
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output axi_awlock,
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output [ 3:0] axi_awcache,
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output [ 2:0] axi_awprot,
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output [ 3:0] axi_awqos,
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output [ 3:0] axi_awuser,
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output [ 7:0] axi_awlen,
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output [ 2:0] axi_awsize,
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output [ 31:0] axi_awaddr,
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input axi_awready,
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output axi_wvalid,
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output [(AXI_DATA_WIDTH-1):0] axi_wdata,
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output [(AXI_DATA_WIDTH/8-1):0] axi_wstrb,
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output axi_wlast,
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output [ 3:0] axi_wuser,
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input axi_wready,
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input axi_bvalid,
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input [ 3:0] axi_bid,
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input [ 1:0] axi_bresp,
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input [ 3:0] axi_buser,
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output axi_bready,
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output axi_arvalid,
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output [ 3:0] axi_arid,
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output [ 1:0] axi_arburst,
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output axi_arlock,
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output [ 3:0] axi_arcache,
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output [ 2:0] axi_arprot,
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output [ 3:0] axi_arqos,
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output [ 3:0] axi_aruser,
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output [ 7:0] axi_arlen,
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output [ 2:0] axi_arsize,
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output [ 31:0] axi_araddr,
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input axi_arready,
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input axi_rvalid,
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input [ 3:0] axi_rid,
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input [ 3:0] axi_ruser,
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input [ 1:0] axi_rresp,
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input axi_rlast,
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input [(AXI_DATA_WIDTH-1):0] axi_rdata,
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output axi_rready);
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localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;
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reg dma_bypass_m1 = 1'b0;
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reg dma_bypass = 1'b0;
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reg dac_bypass_m1 = 1'b0;
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reg dac_bypass = 1'b0;
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reg dac_xfer_out_m1 = 1'b0;
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reg dac_xfer_out_bypass = 1'b0;
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// internal signals
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wire [(AXI_DATA_WIDTH-1):0] axi_rd_data_s;
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wire axi_rd_ready_s;
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wire axi_rd_valid_s;
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wire axi_xfer_req_s;
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wire [31:0] axi_last_addr_s;
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wire [ 3:0] axi_last_beats_s;
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wire axi_dlast_s;
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wire [ 3:0] dma_last_beats_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;
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wire dac_xfer_fifo_out_s;
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wire dac_dunf_fifo_s;
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wire dac_dunf_bypass_s;
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wire dma_ready_wr_s;
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axi_dacfifo_wr #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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.AXI_ADDRESS (AXI_ADDRESS),
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.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
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) i_wr (
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.dma_clk (dma_clk),
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.dma_data (dma_data),
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.dma_ready (dma_ready),
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.dma_ready_out (dma_ready_wr_s),
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.dma_valid (dma_valid),
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.dma_xfer_req (dma_xfer_req),
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.dma_xfer_last (dma_xfer_last),
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.dma_last_beats (dma_last_beats_s),
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.axi_last_addr (axi_last_addr_s),
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.axi_last_beats (axi_last_beats_s),
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.axi_xfer_out (axi_xfer_req_s),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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.axi_awvalid (axi_awvalid),
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.axi_awid (axi_awid),
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.axi_awburst (axi_awburst),
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.axi_awlock (axi_awlock),
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.axi_awcache (axi_awcache),
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.axi_awprot (axi_awprot),
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.axi_awqos (axi_awqos),
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.axi_awuser (axi_awuser),
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.axi_awlen (axi_awlen),
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.axi_awsize (axi_awsize),
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.axi_awaddr (axi_awaddr),
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.axi_awready (axi_awready),
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.axi_wvalid (axi_wvalid),
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.axi_wdata (axi_wdata),
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.axi_wstrb (axi_wstrb),
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.axi_wlast (axi_wlast),
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.axi_wuser (axi_wuser),
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.axi_wready (axi_wready),
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.axi_bvalid (axi_bvalid),
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.axi_bid (axi_bid),
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.axi_bresp (axi_bresp),
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.axi_buser (axi_buser),
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.axi_bready (axi_bready),
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.axi_werror (axi_werror));
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axi_dacfifo_rd #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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.AXI_ADDRESS (AXI_ADDRESS)
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) i_rd (
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.axi_xfer_req (axi_xfer_req_s),
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.axi_last_raddr (axi_last_addr_s),
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.axi_last_beats (axi_last_beats_s),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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.axi_arvalid (axi_arvalid),
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.axi_arid (axi_arid),
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.axi_arburst (axi_arburst),
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.axi_arlock (axi_arlock),
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.axi_arcache (axi_arcache),
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.axi_arprot (axi_arprot),
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.axi_arqos (axi_arqos),
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.axi_aruser (axi_aruser),
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.axi_arlen (axi_arlen),
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.axi_arsize (axi_arsize),
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.axi_araddr (axi_araddr),
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.axi_arready (axi_arready),
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.axi_rvalid (axi_rvalid),
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.axi_rid (axi_rid),
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.axi_ruser (axi_ruser),
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.axi_rresp (axi_rresp),
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.axi_rlast (axi_rlast),
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.axi_rdata (axi_rdata),
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.axi_rready (axi_rready),
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.axi_rerror (axi_rerror),
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.axi_dvalid (axi_rd_valid_s),
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.axi_ddata (axi_rd_data_s),
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.axi_dready (axi_rd_ready_s),
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.axi_dlast (axi_dlast_s));
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axi_dacfifo_dac #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_LENGTH(AXI_LENGTH),
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.DAC_DATA_WIDTH (DAC_DATA_WIDTH)
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) i_dac (
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.axi_clk (axi_clk),
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.axi_dvalid (axi_rd_valid_s),
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.axi_ddata (axi_rd_data_s),
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.axi_dready (axi_rd_ready_s),
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.axi_dlast (axi_dlast_s),
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.axi_xfer_req (axi_xfer_req_s),
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.dma_last_beats (dma_last_beats_s),
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_valid (dac_valid),
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.dac_data (dac_data_fifo_s),
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.dac_xfer_out (dac_xfer_fifo_out_s),
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.dac_dunf (dac_dunf_fifo_s));
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// bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH
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generate
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if (FIFO_BYPASS) begin
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util_dacfifo_bypass #(
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.DAC_DATA_WIDTH (DAC_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH)
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) i_dacfifo_bypass (
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.dma_clk(dma_clk),
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.dma_data(dma_data),
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.dma_ready(dma_ready),
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.dma_ready_out(dma_ready_bypass_s),
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.dma_valid(dma_valid),
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.dma_xfer_req(dma_xfer_req),
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.dac_clk(dac_clk),
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.dac_rst(dac_rst),
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.dac_valid(dac_valid),
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.dac_data(dac_data_bypass_s),
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.dac_dunf(dac_dunf_bypass_s)
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);
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always @(posedge dma_clk) begin
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dma_bypass_m1 <= bypass;
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dma_bypass <= dma_bypass_m1;
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end
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always @(posedge dac_clk) begin
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dac_bypass_m1 <= bypass;
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dac_bypass <= dac_bypass_m1;
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dac_xfer_out_m1 <= dma_xfer_req;
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dac_xfer_out_bypass <= dac_xfer_out_m1;
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end
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// mux for the dma_ready
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always @(posedge dma_clk) begin
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dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s;
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end
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// mux for dac data
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always @(posedge dac_clk) begin
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if (dac_valid) begin
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dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
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end
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dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
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dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
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end
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end else begin /* if (~FIFO_BYPASS) */
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always @(posedge dma_clk) begin
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dma_ready <= dma_ready_wr_s;
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end
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always @(posedge dac_clk) begin
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if (dac_valid) begin
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dac_data <= dac_data_fifo_s;
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end
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dac_xfer_out <= dac_xfer_fifo_out_s;
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dac_dunf <= dac_dunf_fifo_s;
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end
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end
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endgenerate
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endmodule
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