137 lines
4.2 KiB
VHDL
137 lines
4.2 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- Each core or library found in this collection may have its own licensing terms.
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-- The user should keep this in in mind while exploring these cores.
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--
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-- Redistribution and use in source and binary forms,
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-- with or without modification of this file, are permitted under the terms of either
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-- (at the option of the user):
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory, or at:
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-- http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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--
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-- OR
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--
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-- 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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-- http://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axi_ctrlif is
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generic
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(
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C_NUM_REG : integer := 32;
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_FAMILY : string := "virtex6"
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);
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port
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(
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-- AXI bus interface
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s_axi_aclk : in std_logic;
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s_axi_aresetn : in std_logic;
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s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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s_axi_awvalid : in std_logic;
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s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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s_axi_wvalid : in std_logic;
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s_axi_bready : in std_logic;
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s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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s_axi_arvalid : in std_logic;
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s_axi_rready : in std_logic;
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s_axi_arready : out std_logic;
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s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_rresp : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic;
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s_axi_wready : out std_logic;
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s_axi_bresp : out std_logic_vector(1 downto 0);
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s_axi_bvalid : out std_logic;
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s_axi_awready : out std_logic;
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rd_addr : out integer range 0 to C_NUM_REG - 1;
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rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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rd_ack : out std_logic;
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rd_stb : in std_logic;
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wr_addr : out integer range 0 to C_NUM_REG - 1;
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wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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wr_ack : in std_logic;
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wr_stb : out std_logic
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);
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end entity axi_ctrlif;
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architecture Behavioral of axi_ctrlif is
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type state_type is (IDLE, RESP, ACK);
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signal rd_state : state_type;
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signal wr_state : state_type;
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begin
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process (s_axi_aclk)
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begin
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if rising_edge(s_axi_aclk) then
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if s_axi_aresetn = '0' then
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rd_state <= IDLE;
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else
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case rd_state is
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when IDLE =>
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if s_axi_arvalid = '1' then
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rd_state <= RESP;
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rd_addr <= to_integer(unsigned(s_axi_araddr((C_S_AXI_ADDR_WIDTH-1) downto 2)));
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end if;
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when RESP =>
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if rd_stb = '1' and s_axi_rready = '1' then
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rd_state <= IDLE;
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end if;
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when others => null;
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end case;
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end if;
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end if;
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end process;
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s_axi_arready <= '1' when rd_state = IDLE else '0';
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s_axi_rvalid <= '1' when rd_state = RESP and rd_stb = '1' else '0';
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s_axi_rresp <= "00";
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rd_ack <= '1' when rd_state = RESP and s_axi_rready = '1' else '0';
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s_axi_rdata <= rd_data;
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process (s_axi_aclk)
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begin
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if rising_edge(s_axi_aclk) then
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if s_axi_aresetn = '0' then
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wr_state <= IDLE;
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else
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case wr_state is
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when IDLE =>
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if s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_ack = '1' then
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wr_state <= ACK;
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end if;
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when ACK =>
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wr_state <= RESP;
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when RESP =>
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if s_axi_bready = '1' then
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wr_state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process;
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wr_stb <= '1' when s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_state = IDLE else '0';
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wr_data <= s_axi_wdata;
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wr_addr <= to_integer(unsigned(s_axi_awaddr((C_S_AXI_ADDR_WIDTH-1) downto 2)));
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s_axi_awready <= '1' when wr_state = ACK else '0';
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s_axi_wready <= '1' when wr_state = ACK else '0';
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s_axi_bresp <= "00";
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s_axi_bvalid <= '1' when wr_state = RESP else '0';
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end;
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