178 lines
5.2 KiB
Verilog
178 lines
5.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dac_interpolate(
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input dac_clk,
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input dac_rst,
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input [15:0] dac_data_a,
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input [15:0] dac_data_b,
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input dac_valid_a,
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input dac_valid_b,
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output [15:0] dac_int_data_a,
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output [15:0] dac_int_data_b,
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output dac_int_valid_a,
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output dac_int_valid_b,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [ 4:0] up_raddr;
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wire [31:0] interpolation_ratio_a;
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wire [31:0] interpolation_ratio_b;
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wire [ 2:0] filter_mask_a;
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wire [ 2:0] filter_mask_b;
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wire dma_transfer_suspend;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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axi_dac_interpolate_filter i_filter_a (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data (dac_data_a),
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.dac_valid (dac_valid_a),
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.dac_int_data (dac_int_data_a),
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.dac_int_valid (dac_int_valid_a),
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.filter_mask (filter_mask_a),
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.interpolation_ratio (interpolation_ratio_a),
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.dma_transfer_suspend (dma_transfer_suspend)
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);
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axi_dac_interpolate_filter i_filter_b (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data (dac_data_b),
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.dac_valid (dac_valid_b),
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.dac_int_data (dac_int_data_b),
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.dac_int_valid (dac_int_valid_b),
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.filter_mask (filter_mask_b),
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.interpolation_ratio (interpolation_ratio_b),
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.dma_transfer_suspend (dma_transfer_suspend)
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);
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axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
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.clk (dac_clk),
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.dac_interpolation_ratio_a (interpolation_ratio_a),
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.dac_filter_mask_a (filter_mask_a),
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.dac_interpolation_ratio_b (interpolation_ratio_b),
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.dac_filter_mask_b (filter_mask_b),
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.dma_transfer_suspend (dma_transfer_suspend),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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up_axi #(
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.AXI_ADDRESS_WIDTH(7),
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.ADDRESS_WIDTH(5)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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