211 lines
6.9 KiB
Verilog
211 lines
6.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9371_rx_channel #(
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parameter Q_OR_I_N = 0,
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parameter COMMON_ID = 0,
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parameter CHANNEL_ID = 0,
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parameter DATAPATH_DISABLE = 0,
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parameter DATA_WIDTH = 32) (
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// adc interface
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input adc_clk,
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input adc_rst,
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input adc_valid_in,
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input [(DATA_WIDTH-1):0] adc_data_in,
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output adc_valid_out,
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output [(DATA_WIDTH-1):0] adc_data_out,
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input [(DATA_WIDTH-1):0] adc_data_iq_in,
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output [(DATA_WIDTH-1):0] adc_data_iq_out,
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output adc_enable,
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// channel interface
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output up_adc_pn_err,
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output up_adc_pn_oos,
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output up_adc_or,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack);
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localparam NUM_OF_SAMPLES = DATA_WIDTH/16;
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// internal signals
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wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s;
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wire [(DATA_WIDTH-1):0] adc_dfmt_data_s;
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wire [(NUM_OF_SAMPLES-1):0] adc_dcfilter_valid_s;
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wire [(DATA_WIDTH-1):0] adc_dcfilter_data_s;
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wire [(NUM_OF_SAMPLES-1):0] adc_valid_out_s;
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wire adc_pn_err_s;
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wire adc_pn_oos_s;
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wire adc_dfmt_se_s;
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wire adc_dfmt_type_s;
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wire adc_dfmt_enable_s;
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wire adc_dcfilt_enb_s;
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wire [15:0] adc_dcfilt_offset_s;
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wire [15:0] adc_dcfilt_coeff_s;
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wire adc_iqcor_enb_s;
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wire [15:0] adc_iqcor_coeff_1_s;
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wire [15:0] adc_iqcor_coeff_2_s;
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// variables
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genvar n;
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// iq correction inputs
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assign adc_pn_oos_s = 1'b1;
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assign adc_pn_err_s = 1'b0;
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generate
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for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_datafmt
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if (DATAPATH_DISABLE == 1) begin
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assign adc_dfmt_valid_s[n] = adc_valid_in;
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assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in[((16*n)+15):(16*n)];
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end else begin
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ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt (
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.clk (adc_clk),
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.valid (adc_valid_in),
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.data (adc_data_in[((16*n)+15):(16*n)]),
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.valid_out (adc_dfmt_valid_s[n]),
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.data_out (adc_dfmt_data_s[((16*n)+15):(16*n)]),
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.dfmt_enable (adc_dfmt_enable_s),
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.dfmt_type (adc_dfmt_type_s),
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.dfmt_se (adc_dfmt_se_s));
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end
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end
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endgenerate
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generate
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for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_dcfilter
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if (DATAPATH_DISABLE == 1) begin
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assign adc_dcfilter_valid_s[n] = adc_dfmt_valid_s[n];
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assign adc_dcfilter_data_s[((16*n)+15):(16*n)] = adc_dfmt_data_s[((16*n)+15):(16*n)];
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end else begin
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ad_dcfilter i_ad_dcfilter (
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.clk (adc_clk),
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.valid (adc_dfmt_valid_s[n]),
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.data (adc_dfmt_data_s[((16*n)+15):(16*n)]),
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.valid_out (adc_dcfilter_valid_s[n]),
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.data_out (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
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.dcfilt_enb (adc_dcfilt_enb_s),
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.dcfilt_coeff (adc_dcfilt_coeff_s),
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.dcfilt_offset (adc_dcfilt_offset_s));
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end
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end
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endgenerate
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assign adc_valid_out = adc_valid_out_s[0];
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assign adc_data_iq_out = adc_dcfilter_data_s;
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generate
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for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_iqcor
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if (DATAPATH_DISABLE == 1) begin
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assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
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assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
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end else begin
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ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
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.clk (adc_clk),
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.valid (adc_dcfilter_valid_s[n]),
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.data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
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.data_iq (adc_data_iq_in[((16*n)+15):(16*n)]),
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.valid_out (adc_valid_out_s[n]),
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.data_out (adc_data_out[((16*n)+15):(16*n)]),
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.iqcor_enable (adc_iqcor_enb_s),
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.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
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.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
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end
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end
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endgenerate
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up_adc_channel #(
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.COMMON_ID (COMMON_ID),
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.CHANNEL_ID (CHANNEL_ID))
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i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_enable (adc_enable),
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.adc_iqcor_enb (adc_iqcor_enb_s),
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.adc_dcfilt_enb (adc_dcfilt_enb_s),
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.adc_dfmt_se (adc_dfmt_se_s),
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.adc_dfmt_type (adc_dfmt_type_s),
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.adc_dfmt_enable (adc_dfmt_enable_s),
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.adc_dcfilt_offset (adc_dcfilt_offset_s),
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.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
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.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
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.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
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.adc_pnseq_sel (),
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.adc_data_sel (),
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.adc_pn_err (adc_pn_err_s),
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.adc_pn_oos (adc_pn_oos_s),
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.adc_or (1'd0),
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.up_adc_pn_err (up_adc_pn_err),
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.up_adc_pn_oos (up_adc_pn_oos),
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.up_adc_or (up_adc_or),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd16),
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.adc_usr_datatype_bits (8'd16),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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