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pluto_hdl_adi/library/intel
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Istvan Csomortani 0e98527bad intel/adi_jesd204: Expose REGISTER_INPUTS parameter 
Define INPUT_PIPELINE parameter, which can be used to activate the
REGISTER_INPUTS parameter of the PHY. This parameter will add an
additional register stage into the incoming parallel data stream.
It can be used to relax the timing margin between the PHY and Link modules.
 		2020-09-09 14:15:37 +03:00
..
adi_jesd204 intel/adi_jesd204: Expose REGISTER_INPUTS parameter 2020-09-09 14:15:37 +03:00
avl_adxcfg jesd204_framework: Add Stratix10 support 2020-09-09 14:15:37 +03:00
avl_adxcvr avl_adxcvr: Rename variables with alt_* pre-fix 2019-06-29 06:53:51 +03:00
avl_adxcvr_octet_swap library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
avl_adxphy quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
avl_dacfifo intel_mem_asym: Update the interface definitions 2020-08-11 10:14:18 +03:00
axi_adxcvr quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
common axi_ad9361: add_instance command must have a version attribute 2020-08-11 10:14:18 +03:00
jesd204_phy jesd204_framework: Add Stratix10 support 2020-09-09 14:15:37 +03:00
util_clkdiv scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00