158 lines
6.0 KiB
Verilog
158 lines
6.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adrv9009_if (
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// receive
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input adc_clk,
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input [ 3:0] adc_rx_sof,
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input [ 63:0] adc_rx_data,
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input adc_os_clk,
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input [ 3:0] adc_rx_os_sof,
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input [ 63:0] adc_rx_os_data,
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input adc_r1_mode,
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output [ 63:0] adc_data,
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output reg adc_os_valid,
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output reg [127:0] adc_os_data,
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// transmit
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input dac_clk,
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output [127:0] dac_tx_data,
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input [127:0] dac_data);
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// internal signals
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wire [ 63:0] adc_rx_data_s;
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wire [ 63:0] adc_rx_os_data_s;
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wire rx_os_sof;
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// delineating
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assign adc_data[8* 7+:8] = adc_rx_data_s[8* 6+:8];
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assign adc_data[8* 6+:8] = adc_rx_data_s[8* 7+:8];
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assign adc_data[8* 5+:8] = adc_rx_data_s[8* 4+:8];
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assign adc_data[8* 4+:8] = adc_rx_data_s[8* 5+:8];
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assign adc_data[8* 3+:8] = adc_rx_data_s[8* 2+:8];
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assign adc_data[8* 2+:8] = adc_rx_data_s[8* 3+:8];
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assign adc_data[8* 1+:8] = adc_rx_data_s[8* 0+:8];
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assign adc_data[8* 0+:8] = adc_rx_data_s[8* 1+:8];
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assign dac_tx_data[8*15+:8] = dac_data[8*14+:8];
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assign dac_tx_data[8*14+:8] = dac_data[8*15+:8];
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assign dac_tx_data[8*13+:8] = dac_data[8*12+:8];
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assign dac_tx_data[8*12+:8] = dac_data[8*13+:8];
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assign dac_tx_data[8*11+:8] = dac_data[8*10+:8];
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assign dac_tx_data[8*10+:8] = dac_data[8*11+:8];
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assign dac_tx_data[8* 9+:8] = dac_data[8* 8+:8];
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assign dac_tx_data[8* 8+:8] = dac_data[8* 9+:8];
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assign dac_tx_data[8* 7+:8] = dac_data[8* 6+:8];
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assign dac_tx_data[8* 6+:8] = dac_data[8* 7+:8];
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assign dac_tx_data[8* 5+:8] = dac_data[8* 4+:8];
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assign dac_tx_data[8* 4+:8] = dac_data[8* 5+:8];
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assign dac_tx_data[8* 3+:8] = dac_data[8* 2+:8];
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assign dac_tx_data[8* 2+:8] = dac_data[8* 3+:8];
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assign dac_tx_data[8* 1+:8] = dac_data[8* 0+:8];
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assign dac_tx_data[8* 0+:8] = dac_data[8* 1+:8];
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// instantiations
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always @(posedge adc_os_clk) begin
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if (adc_r1_mode == 1'b1) begin
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adc_os_valid <= 'd1;
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adc_os_data[8* 7+:8] <= adc_rx_os_data_s[8* 6+:8];
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adc_os_data[8* 6+:8] <= adc_rx_os_data_s[8* 7+:8];
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adc_os_data[8* 5+:8] <= adc_rx_os_data_s[8* 4+:8];
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adc_os_data[8* 4+:8] <= adc_rx_os_data_s[8* 5+:8];
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adc_os_data[8* 3+:8] <= adc_rx_os_data_s[8* 2+:8];
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adc_os_data[8* 2+:8] <= adc_rx_os_data_s[8* 3+:8];
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adc_os_data[8* 1+:8] <= adc_rx_os_data_s[8* 0+:8];
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adc_os_data[8* 0+:8] <= adc_rx_os_data_s[8* 1+:8];
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adc_os_data[127:64] <= 64'h0;
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end else begin
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adc_os_valid <= !adc_os_valid;
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if (adc_os_valid == 1'b1) begin
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adc_os_data[8*13+:8] <= adc_rx_os_data_s[8* 6+:8];
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adc_os_data[8*12+:8] <= adc_rx_os_data_s[8* 7+:8];
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adc_os_data[8* 9+:8] <= adc_rx_os_data_s[8* 4+:8];
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adc_os_data[8* 8+:8] <= adc_rx_os_data_s[8* 5+:8];
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adc_os_data[8* 5+:8] <= adc_rx_os_data_s[8* 2+:8];
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adc_os_data[8* 4+:8] <= adc_rx_os_data_s[8* 3+:8];
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adc_os_data[8* 1+:8] <= adc_rx_os_data_s[8* 0+:8];
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adc_os_data[8* 0+:8] <= adc_rx_os_data_s[8* 1+:8];
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end else begin
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adc_os_data[8*15+:8] <= adc_rx_os_data_s[8* 6+:8];
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adc_os_data[8*14+:8] <= adc_rx_os_data_s[8* 7+:8];
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adc_os_data[8*11+:8] <= adc_rx_os_data_s[8* 4+:8];
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adc_os_data[8*10+:8] <= adc_rx_os_data_s[8* 5+:8];
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adc_os_data[8* 7+:8] <= adc_rx_os_data_s[8* 2+:8];
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adc_os_data[8* 6+:8] <= adc_rx_os_data_s[8* 3+:8];
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adc_os_data[8* 3+:8] <= adc_rx_os_data_s[8* 0+:8];
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adc_os_data[8* 2+:8] <= adc_rx_os_data_s[8* 1+:8];
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end
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end
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end
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genvar n;
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generate
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for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
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ad_xcvr_rx_if i_xcvr_rx_if (
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.rx_clk (adc_clk),
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.rx_ip_sof (adc_rx_sof),
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.rx_ip_data (adc_rx_data[n*32+:32]),
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.rx_sof (),
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.rx_data (adc_rx_data_s[n*32+:32]));
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ad_xcvr_rx_if i_xcvr_rx_os_if (
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.rx_clk (adc_os_clk),
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.rx_ip_sof (adc_rx_os_sof),
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.rx_ip_data (adc_rx_os_data[n*32+:32]),
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.rx_sof (rx_os_sof),
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.rx_data (adc_rx_os_data_s[n*32+:32]));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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