325 lines
9.7 KiB
Verilog
325 lines
9.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_mc_speed
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#(
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parameter C_S_AXI_MIN_SIZE = 32'hffff,
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parameter C_BASEADDR = 32'hffffffff,
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parameter C_HIGHADDR = 32'h00000000,
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parameter MOTOR_CONTROL_REVISION = 2
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)
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//----------- Ports Declarations -----------------------------------------------
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(
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// physical interface
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input [2:0] position_i,
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input [2:0] bemf_i,
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output [2:0] position_o,
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output [31:0] speed_o,
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output new_speed_o,
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input [1:0] hall_bemf_i,
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input ref_clk,
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// dma interface
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output adc_clk_o,
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output adc_dwr_o,
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output [31:0] adc_ddata_o,
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input adc_dovf_i,
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input adc_dunf_i,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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// debug signals
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output adc_mon_valid,
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output [31:0] adc_mon_data);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg adc_valid = 'd0;
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reg [31:0] adc_data = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 'd0;
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire adc_start_s;
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wire [31:0] speed_data_s;
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wire adc_enable_s;
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wire adc_status_s;
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_adc_common_rdata_s;
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wire up_adc_common_ack_s;
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wire [31:0] pid_s;
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wire [ 2:0] position_s;
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wire [ 2:0] bemf_s;
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wire [ 2:0] bemf_delayed_s;
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wire new_speed_s;
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wire [ 2:0] bemf_multiplex_s;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_clk_o = ref_clk;
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assign adc_dwr_o = adc_valid;
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assign adc_ddata_o = adc_data;
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// monitor signals
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assign adc_mon_valid = new_speed_s;
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assign adc_mon_data = { 20'h0, bemf_multiplex_s, bemf_s, bemf_delayed_s, position_s };
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assign bemf_multiplex_s =(MOTOR_CONTROL_REVISION == 2) ? position_i : bemf_i;
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assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s;
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assign new_speed_o = new_speed_s;
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assign speed_o = speed_data_s;
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// adc channels - dma interface
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always @(posedge ref_clk)
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begin
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adc_data <= speed_data_s;
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adc_valid <= new_speed_s;
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk)
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begin
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if(up_rstn == 0)
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begin
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up_rdata <= 'd0;
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up_ack <= 'd0;
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end else
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begin
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up_rdata <= up_adc_common_rdata_s;
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up_ack <= up_adc_common_ack_s;
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end
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end
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// HALL sensors debouncers
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debouncer
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#( .DEBOUNCER_LEN(400))
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position_0(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(position_i[0]),
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.sig_o(position_s[0]));
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debouncer
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#( .DEBOUNCER_LEN(400))
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position_1(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(position_i[1]),
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.sig_o(position_s[1]));
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debouncer
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#( .DEBOUNCER_LEN(400))
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position_2(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(position_i[2]),
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.sig_o(position_s[2]));
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// BEMF debouncer
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debouncer
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#( .DEBOUNCER_LEN(400))
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bemf_0(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(bemf_multiplex_s[0]),
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.sig_o(bemf_s[0]));
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debouncer
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#( .DEBOUNCER_LEN(400))
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bemf_1(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(bemf_multiplex_s[1]),
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.sig_o(bemf_s[1]));
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debouncer
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#( .DEBOUNCER_LEN(400))
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bemf_2(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(bemf_multiplex_s[2]),
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.sig_o(bemf_s[2]));
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delay_30_degrees delay_30_degrees_i1(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.offset_i(32'h0),
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.position_i(bemf_s),
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.position_o(bemf_delayed_s));
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speed_detector
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#( .AVERAGE_WINDOW(1024),
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.LOG_2_AW(10),
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.SAMPLE_CLK_DECIM(1000))
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speed_detector_inst(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.position_i(position_o),
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.new_speed_o(new_speed_s),
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.current_speed_o(),
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.speed_o(speed_data_s));
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// common processor control
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up_adc_common i_up_adc_common(
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.mmcm_rst(),
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.adc_clk(ref_clk),
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.adc_rst(adc_rst),
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.adc_r1_mode(),
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.adc_ddr_edgesel(),
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.adc_pin_mode(),
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.adc_status(1'b1),
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.adc_status_ovf(adc_dovf_i),
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.adc_status_unf(adc_dunf_i),
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.adc_clk_ratio(32'd1),
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.delay_clk(1'b0),
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.delay_rst(),
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.delay_sel(),
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.delay_rwn(),
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.delay_addr(),
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.delay_wdata(),
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.delay_rdata(5'd0),
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.delay_ack_t(1'b0),
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.delay_locked(1'b0),
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.drp_clk(1'd0),
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.drp_rst(),
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.drp_sel(),
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.drp_wr(),
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.drp_addr(),
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.drp_wdata(),
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.drp_rdata(16'd0),
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.drp_ready(1'b0),
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.drp_locked(1'b0),
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.up_usr_chanmax(),
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.adc_usr_chanmax(8'd0),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_adc_common_rdata_s),
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.up_ack(up_adc_common_ack_s)
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);
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// up bus interface
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up_axi #(
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.PCORE_BASEADDR(C_BASEADDR),
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.PCORE_HIGHADDR(C_HIGHADDR))
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i_up_axi(
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_rdata),
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.up_ack(up_ack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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