Istvan Csomortani ac2e5a9dac constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.		2017-02-24 13:43:32 +02:00
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common	ad6676evb: Update projects with ad_sysref_gen	2016-12-19 10:52:25 +00:00
vc707	constraints: Update constraints	2017-02-24 13:43:32 +02:00
zc706	constraints: Update constraints	2017-02-24 13:43:32 +02:00
Makefile	Makefile: Added top level Makefile. Modified behavior of clean and clean-all	2015-04-17 17:22:38 +03:00