zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,849 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Lars-Peter Clausen 0a72693d4d adi_board.tcl: ad_xcvrcon: Handle ADI JESD204 core 
Let the ad_xcvrcon handle the ADI JESD204 link layer cores. The function
will detect the JESD204 core vendor and connect the appropriate signals
based on it. This means it can still be used with the Xilinx JESD204 core
as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-05-23 11:16:07 +02:00
library Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
projects adi_board.tcl: ad_xcvrcon: Handle ADI JESD204 core 2017-05-23 11:16:07 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects

Branches

Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.

Latest Release Notes

HDL User Guide

HDL Help & Support