131 lines
4.6 KiB
Verilog
131 lines
4.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_dds_1 (
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// interface
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clk,
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angle,
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scale,
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dds_data);
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// interface
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input clk;
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input [15:0] angle;
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input [15:0] scale;
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output [15:0] dds_data;
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// internal registers
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reg sine_sign = 'd0;
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reg [14:0] sine_magn = 'd0;
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reg [14:0] sine_scale_p = 'd0;
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reg [14:0] sine_scale_n = 'd0;
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reg sine_scale_sign = 'd0;
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reg [15:0] dds_data = 'd0;
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// internal signals
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wire [15:0] sine_s;
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wire [14:0] sine_p_s;
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wire [14:0] sine_n_s;
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wire [31:0] sine_scale_s;
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wire sine_sign_s;
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wire scale_sign_s;
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wire [14:0] sine_scale_p_s;
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wire [14:0] sine_scale_n_s;
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wire sine_scale_sign_s;
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// sine generator
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ad_dds_sine #(.DELAY_DATA_WIDTH(1)) i_dds_sine (
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.clk (clk),
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.angle (angle),
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.sine (sine_s),
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.ddata_in (1'b0),
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.ddata_out ());
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// sign-magnitude
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assign sine_p_s = sine_s[14:0];
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assign sine_n_s = ~sine_s[14:0] + 1'b1;
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always @(posedge clk) begin
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sine_sign <= sine_s[15];
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if (sine_s[15] == 1'b1) begin
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sine_magn <= sine_n_s;
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end else begin
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sine_magn <= sine_p_s;
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end
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end
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// scale
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ad_mul_u16 #(.DELAY_DATA_WIDTH(2)) i_mul_u16 (
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.clk (clk),
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.data_a ({1'b0, sine_magn}),
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.data_b ({1'b0, scale[14:0]}),
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.data_p (sine_scale_s),
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.ddata_in ({sine_sign, scale[15]}),
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.ddata_out ({sine_sign_s, scale_sign_s}));
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assign sine_scale_p_s = sine_scale_s[28:14];
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assign sine_scale_n_s = ~sine_scale_s[28:14] + 1'b1;
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assign sine_scale_sign_s = sine_sign_s ^ scale_sign_s;
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always @(posedge clk) begin
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sine_scale_p <= sine_scale_p_s;
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sine_scale_n <= sine_scale_n_s;
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sine_scale_sign <= sine_scale_sign_s;
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if (sine_scale_sign == 1'b1) begin
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dds_data <= {1'b1, sine_scale_n};
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end else begin
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dds_data <= {1'b0, sine_scale_p};
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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