Adrian Costina 8476d9d59a axi_logic_analyzer: Allow only data[0] to be used as alternative clock. ... - drive all logic on clk_out instead of clk		2017-04-18 12:17:39 +02:00
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Makefile	axi_logic_analyzer: Initial commit	2017-01-31 16:23:56 +02:00
axi_logic_analyzer.v	axi_logic_analyzer: Allow only data[0] to be used as alternative clock.	2017-04-18 12:17:39 +02:00
axi_logic_analyzer_constr.xdc	axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching	2017-02-27 14:19:54 +02:00
axi_logic_analyzer_ip.tcl	library: Delete all adi_ip_constraint process call	2017-04-06 12:36:47 +03:00
axi_logic_analyzer_reg.v	axi_logic_analyzer: Initial commit	2017-01-31 16:23:56 +02:00
axi_logic_analyzer_trigger.v	axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path	2017-03-14 18:00:42 +02:00