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pluto_hdl_adi/library/spi_engine
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Istvan Csomortani 07956cfe66 spi_engine: Define parameter inside the module statement 
Part of the effort to update all verilog files to use the
ANSI-C style port list in module definitions. (verilog-2001)
 		2017-05-04 12:13:47 +03:00
..
axi_spi_engine spi_engine: Define parameter inside the module statement 2017-05-04 12:13:47 +03:00
interfaces interface: Update spi_engine_offload_ctrl definition 2017-04-27 11:19:22 +03:00
spi_engine_execution spi_engine: Define parameter inside the module statement 2017-05-04 12:13:47 +03:00
spi_engine_interconnect spi_engine: Define parameter inside the module statement 2017-05-04 12:13:47 +03:00
spi_engine_offload spi_engine: Define parameter inside the module statement 2017-05-04 12:13:47 +03:00