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Istvan Csomortani 051ac307e6 daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk 2016-02-15 19:26:58 +02:00
library axi_ad9684: Fix constraint file 2016-02-12 14:38:59 +02:00
projects daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk 2016-02-15 19:26:58 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore ignore gui 2015-09-22 16:32:02 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update Vivado's version number 2015-09-29 15:11:10 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.